AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.1.3. AXI Streaming Intel® FPGA IP for PCI Express* Interface Attributes

The register indicates the AXI Streaming Intel® FPGA IP for PCI Express* interface attributes settings during compile time.

Default Value: Set As per Parameter Settings

Table 74.   AXI Streaming Intel® FPGA IP for PCI Express* Interface Attributes
Register Name Bit Attribute User Side Description
IP Interface Attributes 3-0 RO Reflects AXI-ST Initiator Interface ready_latency setting
7-4 RO Reserved
11-8 RO Reflects AXI-MM Initiator Interface ready_latency setting
14-12 RO

Indicates AXI-ST Interface Width

000 - 32 bits

001 - 64 Bits

010 - 128 Bits

011 - 256 Bits

100 - 512 Bits

All others - Reserved

17-15 RO

Indicates AXI-Lite Interface Width

000 - 32 bits

001 - 64 Bits

Reserved

20-18 RO

Reserved

31-21 RO Reserved