Visible to Intel only — GUID: kai1698164119646
Ixiasoft
Visible to Intel only — GUID: kai1698164119646
Ixiasoft
3.7. Compile the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
You must complete the following steps to compile the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant.
AXI Streaming Intel® FPGA IP for PCI Express* in | Description |
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Standalone mode | Use the Quartus Prime Pro software -> Processing menu to select Start Compilation. Timing can be verified using the TimeQuest Timing Analyzer of the Quartus Prime Pro. Use the assembler to generate the configuration bit stream as a .sof (or .pof) file. This file is what you download to a board to perform hardware verification. |
Design example |
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Intel Open FPGA Stack (OFS) reference design | Pre-compiled OFS design with IP and example workloads are provided as part of the reference design.
Note: Contact your Intel Sales Representative for access to the Intel OFS design repository.
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Download the bit stream resulting from the compilation onto the device and bring up the PCIe* link(s) in the design. You can find your compilation project files inside the <project_dir>/<AXI Streaming IP path>/output_files folder. Ensure that your device is linked up and enumerated in the PCI Express* topology. For examples on how to obtain general information of the device such as link speed, link width, and more, refer to Operating System Tools and Utilities. You can use utilities like lspci, setpci to obtain general information of the device like link speed, link width, etc.
For more details, refer to Operating System Tools and Utilities.
Use the steps below to compile the IP when using the Quartus generated design.