AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

4.15. TX Non-Posted Metering Requirement on Application

The PCIe* HIP implements a finite number of RX Completion Buffers for its header and data. However, in endpoint mode, it advertises infinite credit to the host. Hence, the application logic needs to implement metering logic on its TX Non-Posted requests such that it does not issue more requests than allowed to avoid overflowing the completion buffer. Refer to the Appendix sections for detailed completion buffer sizes for each different tile.