AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.3.6. Application Packet Transmit Interface (st_tx)

The outbound packet towards the link from application side is transmitted through this interface with separate header and data interfaces. The PCIe header, PF Number, VF Number, BAR number and Prefix information are grouped as a 32-byte header on the AXI Streaming interface. The data is presented as a 1024-, 512- or 256-bit wide data bus, segmented into a number of segments depending on the configuration (Gen3/4/5 x16/x8x8) and mode (HIP Native, Simple or Compact packing) used.
Table 50.  APP AXI ST TX Interface
Signal Name Direction Clock Domain Description
app_ss_st_tx_tvalid Input axi_st_clk app_ss_st_tx_valid indicates that the source is driving a valid transfer.
ss_app_st_tx_tready Output axi_st_clk

app_axi_st_tx_ready indicates that the sink can accept a transfer in the current cycle.

readyLatency parameter defined in Avalon spec shall be supported. By default, the value is '0'.

app_ss_st_tx_tdata[(DWIDTH*NUM_OF_SEG)-1:0] Input axi_st_clk

Data Interface with configurable width specified by the DWIDTH_SEG*NUM_OF_SEG parameter.

tdata carries only the payload.

Default DWIDTH = DWIDTH_SEG*NUM_OF_SEG = 1024.

app_ss_st_tx_tkeep[((DWIDTH_SEG/8)*NUM_OF_SEG)-1:0] Input axi_st_clk

A byte qualifier used to indicate whether the content of the associated byte is valid.

The invalid bytes are allowed only during app_axi_st_tx_tlast cycle.

app_ss_st_tx_tlast Input axi_st_clk Indicates End of Data/Command Transmission.
ss_app_st_tx_tuser_last_segment[NUM_OF_SEG-1:0] Input axi_st_clk Indicates the last segment of the packet. Not applicable for the Simple packing scheme. For a header without payload, this signal is asserted during the header cycle.
ss_app_st_tx_tuser_vendor[NUM_OF_SEG-1:0] Input axi_st_clk

Vendor Specific Tuser bits.

Indicates Header Format.

Reserved (don't-care).

ss_app_st_tx_tuser_hvalid[NUM_OF_SEG-1:0] Input axi_st_clk Indicates the tuser_hdr and tuser_vendor bits are valid in the respective segment.
app_ss_st_tx_tuser_hdr[256*NUM_OF_SEG-1:0] Input axi_st_clk Carries header format for the respective segment. Refer to Header Format for the bit positions and mapping.

Refer to the section Data and Header Packing Schemes for timing diagrams in each of the modes when using the Application Packet Transmit Interface.