AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

3.4.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example

The SR-IOV design example performs memory transfers from a host processor to a target device. It supports up to two Physical Functions (PFs) and 32 Virtual Functions (VFs) per PF. Note that this design example does not support back-to-back transactions from the host processor since the design is intended to showcase single-dword transactions. In addition, the addresses for all the transactions must be dword-aligned.

This design example automatically creates the files necessary to simulate and compile in the Quartus® Prime software. You can download the compiled design to an Agilex™ 7 I-Series FPGA Development Kit.

Table 11.  SR-IOV AXI Streaming Design Example Supported Configurations (P-Tile)Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Port Mode Link Width Link Speed HIP Data Width (Bits) Application Data Width (Bits) Compact/HIP Native Mode Design Example Support
Endpoint x16 Gen4 512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
Gen3 512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
x8 Gen4 256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
Gen3 256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
x4 Gen4 128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Gen3 128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Root Port N/A N/A N/A N/A N/A N/A
TL Bypass N/A N/A N/A N/A N/A N/A
PIPE Direct (PIPE-D) N/A N/A N/A N/A N/A N/A
Note: For the P-Tile AXI Streaming SR-IOV design example, only VCS, VCSMX, Questasim, and Modelsim are supported for simulation.
Table 12.  SR-IOV AXI Streaming Design Example Supported Configurations (F-Tile)Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Port Mode Link Width Link Speed HIP Data Width (Bits) Application Data Width (Bits) Compact/HIP Native Mode Design Example Support
Endpoint x16 Gen4 512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
Gen3 512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
x8 Gen4 256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
Gen3 256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
x4 Gen4 128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Gen3 128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Root Port   N/A N/A N/A N/A N/A
TL Bypass   N/A N/A N/A N/A N/A
PIPE Direct (PIPE-D)   N/A N/A N/A N/A N/A
Note: For the F-Tile AXI Streaming SR-IOV design example in Endpoint mode, only VCS, VCSMX, Questasim, and Modelsim are supported for simulation.
Table 13.  SR-IOV AXI Streaming Design Example Supported Configurations (R-Tile)Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Port Mode Link Width Link Speed HIP Data Width (Bits) Application Data Width (Bits) Compact/HIP Native Mode Design Example Support
Endpoint x16 Gen5 1024 (4 x 256) 1024 (4 x 256) HIP Native SCTH
1024 (4 x 256) 1024 (4 x 256) Compact SCTH
1024 (4 x 256) 1024 (2 x 512) Compact SCTH
1024 (4 x 256) 1024 (1 x 1024) Compact SCTH
1024 (4 x 256) 512 (2 x 256) Compact SCTH
1024 (4 x 256) 512 (1 x 512) Compact SCTH
1024 (4 x 256) 256 ( 1 x 256) Compact SCTH
Gen4 1024 (4 x 256) 1024 (4 x 256) HIP Native SCTH
512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) HIP Native SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
Gen3 1024 (4 x 256) 1024 (4 x 256) HIP Native SCTH
512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) HIP Native SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
x8 Gen5 512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) HIP Native SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
Gen4 512 (2 x 256) 512 (2 x 256) HIP Native SCTH
256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) HIP Native SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
Gen3 512 (2 x 256) 512 (2 x 256) HIP Native SCTH
256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) HIP Native SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
x4 Gen5 256 (2 x 128) 1024 (4 x 256) Compact CTH
256 (2 x 128) 1024 (2 x 512) Compact CTH
256 (2 x 128) 1024 (1 x 1024) Compact CTH
256 (2 x 128) 512 (2 x 256) Compact CTH
256 (2 x 128) 512 (1 x 512) Compact CTH
256 (2 x 128) 256 (2 x 128) HIP Native CTH
256 (2 x 128) 256 (2 x 128) Compact CTH
256 (2 x 128) 256 (1 x 256) Compact CTH
Gen4 256 (2 x 128) 256 (2 x 128) HIP Native (4x4, 1x4) CTH
128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) HIP Native CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Gen3 256 (2 x 128) 256 (2 x 128) HIP Native (4x4, 1x4) CTH
128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) HIP Native CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Root Port N/A N/A N/A N/A N/A N/A
TL Bypass N/A N/A N/A N/A N/A N/A
PIPE Direct (PIPE-D) N/A N/A N/A N/A N/A N/A
Note: For the R-Tile AXI Streaming SR-IOV design example in Endpoint mode, only VCS, and VCSMX are supported for simulation.
Note: The R-Tile AXI Streaming SR-IOV design example in PIPE Direct mode is only supported by VCS.
Figure 12. SR-IOV AXI Streaming 1x16, 1x8, 1x4 Design Example Block Diagram
Figure 13. SR-IOV AXI Streaming 2x8, 2x4 Design Example Block Diagram
Figure 14. SR-IOV AXI Streaming 4x4 Design Example Block Diagram