AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.7. Control Shadow Interface (st_ctrlshadow)

The control shadow interface is used to bring out the settings of the various configuration register fields of the function. These fields are often required in designing the control path of the application layer logic.

The application logic decodes information provided on this interface to create a shadow copy. The interface provides update to primary control signals only. The application logic must read extra information required through lite_csr interface by reading configuration register of interest. The sections below explain additional information required by application.

Bus Master Enable

The application logic requires the BME information to determine if it can generate request for a particular function. Each function in the application logic cannot generate bus master requests unless its corresponding BME is set. The application logic monitors control shadow interface for BME event for this purpose. Since PCIe* SS does not autonomously generate bus master request by itself, it will not qualify the transmit path with BME settings and solely relies on application.

MSI Enable

The application logic requires MSI Address and MSI Data information from MSI capability to generate MSI interrupt. The application logic monitors control shadow interface for MSI Enable event to read this additional information from MSI capability.

VF Enable

The Virtual Function in application logic cannot generate any traffic unless they are enabled by HOST. The number of VFs enabled can be different than number of VFs advertised as initial VFs. The application logic can find number of VFs visible by reading NumVFs register in SRIOV capability. The read of this register must be triggered after VF Enable bit is set by HOST.

TPH Req Enable

The function can support all operational modes of TPH, no ST mode, interrupt vector mode or device specific mode. The HOST communicates mode of operation by writing ST Mode Select bits in TPH requester control register. The application reads this register and generates traffic only when TPH requester enable bit is set.

ATS Enable

The function can read Smallest Translation Unit field from ATS control register when ATS enable bit is set.

Table 61.  Control Shadow Interface
Signal Name Direction Clock Domain Description
ss_app_st_ctrlshadow_tvalid Output axi_lite_clk The IP asserts this output for one clock cycle when there is an update to the register fields being monitored, because of a Configuration Write performed by the Root Comple.g., The user can copy the new settings of the register fields from the tdata bus.
ss_app_st_ctrlshadow_tdata[39:0] Output axi_lite_clk

When app_ctrl_shadow_tvalid has been asserted, this output provides the current settings of the register fields of the associated Function.

[2:0] - Identifies the physical function Number of configuration register

[13:3] - Identifies the virtual function Number of configuration register

[14] - Indicates information is for Virtual Function implemented in slot's physical function

[19:15] - Identifies the slot Number of configuration register

[20] - Bus Master Enable

[21] - MSI-X Mask

[22] - MSI-X Enable

[23] - Mem Space Enable

[24] - ExpRom Enable

[25] - TPH Req Enable

[26] - ATS Enable

[27] - MSI Enable

[28] - MSI Mask

[29] - Extended Tag

[30] - 10 Bit Tag Req Enable

[31] - PTM Enable

[34:32] - MPS Size

[37:35] - MRRS Size

[38] - VF Enable

[39] - Page Request Enable

ATS Enable Timing Diagram

The following figure shows output on the Control Shadow interface when there is an update to the control shadow bits in the HIP configuration register.

Figure 57. ATS Enable Timing Diagram