AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

4.3. HIP Interface (IF) Adaptor

The Hard IP (HIP) interfaces with the HIP IF Adaptor in the AXI Streaming Intel® FPGA IP for PCI Express* . The HIP IF adaptor acts as an interface between the HIP and the downstream logic. The HIP IF Adaptor provides a standardized interface to the downstream logic by performing the required width and format adaptation depending on the AVST and sideband interfaces of the tile. The clock domain crossing module allows downstream logic to run at different frequencies.

Figure 32. Hard IP IF Adaptor