AXI Streaming Intel® FPGA IP for PCI Express* User Guide
Visible to Intel only — GUID: hmr1698271685561
Ixiasoft
Visible to Intel only — GUID: hmr1698271685561
Ixiasoft
4.4. Application Error Reporting
The IP implements Error Interface (st_err) registers allowing you to indicate various errors. The IP logic then forwards this error information to the HIP block. The HIP block then responds to the assertion of these error bits by performing the following:
- Logging the status in the error reporting registers of the Function.
- Sending error messages as per Basic Error Reporting policies or as per AER policies.
The following figure shows registers implemented in the IP register space for error reporting. Refer to Register Descriptions for more details on the AER registers.