AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.2.2. HIP BP CYCLES

The register indicates back pressure cycles observed because HIP transmit interface was not ready to accept transaction.

Figure 62. HIP BP Cycles

Default Value: 0x0000_0000

Table 87.  IP Interface attributes
Register Name Bit Attribute User Side Description
HIP BP CYCLES 30-0 RW1C Back Pressure Cycle Count
31 RW1C Indicates Overflow, cycle count reached 31'h7FFFFFFFF