AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.3.5.3. Simple Packing

This packing scheme allows the header to be packed on segment0 for any given clock cycle. This constrains the design to send one packet per cycle. This is applicable to P/F/R-Tiles. When using R-Tile, the simple packing scheme is only available when using the non-HIP Native mode.
Note: This mode is not supported in the current Quartus® Prime release.