AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

4.4. Application Error Reporting

The IP implements Error Interface (st_err) registers allowing you to indicate various errors. The IP logic then forwards this error information to the HIP block. The HIP block then responds to the assertion of these error bits by performing the following:

  • Logging the status in the error reporting registers of the Function.
  • Sending error messages as per Basic Error Reporting policies or as per AER policies.

The following figure shows registers implemented in the IP register space for error reporting. Refer to Register Descriptions for more details on the AER registers.

Figure 33. Error Reporting
Note: VF-related errors detected in application layer cannot be logged in HIP status registers as HIP's Application Error Interface doesn't provide error handling down to VF granularity. Additionally, the Hard IP Reconfiguration Interface doesn't provide access to set Error Status registers. In summary, VF related errors reported through the Application Error Reporting registers will not have any effect.