AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.1.12. MSI PENDING CTRL

The application layer uses both MSI PENDING CTRL and MSI PENDING registers to update the MSI Pending Bits for each function.

Default Value: 0x0000_0000

Table 83.  MSI Pending Control Register
Register Name Bit Attribute User Side Description
MSI PENDING CTRL 0 RW

Update MSI Pending Bits

Writing '1' to this bit causes an update to the MSI Pending.

Bits based on MSI PENDING value.

Write to this bit is ignored if bit is already set.

The IP clears this bit indicating the requested update is complete.

5-1 RW

PF Number

Indicates Physical Function Number of the update request.

Note: Current Quartus release limits to max 8 PFs only.
6 RsvdZ Reserved
17-7 RW

VF Number

Indicates Virtual Function Number of the update request.

18 RsvdZ Reserved
19 RW

VF Active

Indicates Virtual Function is the target of the update request.

24-20 RW

Slot Number

Indicates Slot Number of the update request.

31-25 RsvdZ Reserved