AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

4.2. PCIe Hard IP (HIP)

The PCIe* Hard IP implements the functionality of the PCIe* protocol. The HIP implements Physical, Data Link and Transaction Layers of the protocol. The HIP handles link training, DLLP exchanges, credit handling, BAR decode, and error handling in normal mode. It also implements SRIOV functionality for handling virtualization. The HIP’s main data path interface is the Avalon Streaming interface.

Figure 31.  PCIe* Hard IP