AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.3.7. Application Packet Receive Interface (st_rx)

The packet received from the link is presented to the application logic on this interface with separate header and data interfaces. The PCIe header, PF Number, VF Number, BAR number and Prefix information are grouped as a 32-byte header on the AXI Streaming interface. The data is presented as a 1024-, 512- or 256-bit wide data bus, segmented into a number of segments depending on the configuration (Gen3/4/5 x16/x8x8) and mode (HIP Native, Simple or Compact packing) used.
Signal Name Direction Clock Domain Description
ss_app_st_rx_tvalid Output axi_st_clk ss_app_st_rx_tvalid indicates that the source is driving a valid transfer.
app_ss_st_rx_tready Input axi_st_clk app_ss_st_rx_tready indicates that the sink can accept a transfer in the current cycle readyLatency parameter defined in Avalon spec shall be supported. By default, the value is '0'.
ss_app_st_rx_tdata[(DWIDTH_SEG*NUM_OF_SEG)-1:0] Output axi_st_clk

Data interface with configurable width specified by the DWIDTH_SEG*NUM_OF_SEG parameter.

Default DWIDTH = DWIDTH_SEG*NUM_OF_SEG = 1024

tdata carries only the payload.

ss_app_st_rx_tkeep[((DWIDTH_SEG/8)*NUM_OF_SEG)-1:0] Output axi_st_clk

A byte qualifier used to indicate whether the content of the associated byte is valid. The invalid bytes are allowed only during the ss_app_st_tx_tlast cycle.

ss_app_st_rx_tlast Output axi_st_clk

Indicates End of Data/Command Transmission.

tlast may seem redundant with the tuser.last_segment. However, tlast can be used by the front-end layer of the AXI BFM/routing fabric that does not deal with the decoding of the multipacket data.

ss_app_st_rx_tuser_last_segment[NUM_OF_SEG-1:0] Output axi_st_clk

Indicates Packet End position on tdata bus.

Only applicable with Variable Header Position and Compact Packing scheme.

Note: Variable and compact packing not currently supported.
ss_app_st_rx_tuser_vendor[NUM_OF_SEG-1:0] Output axi_st_clk

Vendor Specific Tuser bits.

Indicates Header Format.

Is a don't-care in Power User mode.

[0] - Indicates Header format of First packet in a cycle

[1] - Indicates Header format of Second packet in a cycle

ss_app_st_rx_tuser_hvalid[NUM_OF_SEG-1:0] Output axi_st_clk

Indicates the ss_app_st_rx_tuser_hdr and ss_app_st_rx_tuser_vendor bits are valid in the respective segment.

ss_app_st_rx_tuser_hdr[NUM_OF_SEG*256-1:0] Output axi_st_clk

If tuser_vendor = 0, tuser_hdr carries the Power User Mode header format for the respective segment.

If tuser_vendor = 1, tuser_dr carries the header format for the respective segment.

Refer to the section Data and Header Packing Schemes for timing diagrams in each of the modes when using the Application Packet Receive Interface.