AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.8. Completion Timeout Interface (st_cplto)

The completion timeout interface indicates completion timeout event to application. The interface provides the function number and tag number of the outstanding request timed out.

Table 62.  Completion Timeout Interface
Signal Name Direction Clock Domain Description
ss_app_st_cplto_tvalid Output axi_lite_clk tvalid indicates that the completion timeout received for outstanding NP request.
ss_app_st_cplto_tdata[29:0] Output axi_lite_clk

Carries completion Timeout Information

[9:0] - Tag Number

[12:10] - PF Number, indicates parent PF number of VF when VF Active is high else PF Number of function

[23:13] - VF Number, indicates VF number when VF Active js high

[24] - VF Active, Indicates timeout is for VF

[29:25] always 0. Reserved

Figure 58. Completion Timeout Interface Timing Diagram