AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

A.2.1. F-Tile Completion Buffer Size

For F-Tile, the PCIe Hard IP implements Completion Buffers for Header and Data for each PCIe core/port. In Endpoint mode, when Completion credits are infinite, user application needs to manage the number of outstanding requests according to the buffer size to prevent overflow and lost Completions packets.

Table 107.  F-Tile Completion Buffer Size
Completion Buffer Depth Width
Port 0 Cpl Header 1144 128
Port 0 Cpl Data 1444 256
Port 1 Cpl Header 572 128
Port 1 Cpl Data 1444 128
Port 2 Cpl Header 286 128
Port 2 Cpl Data 1444 64
Port 3 Cpl Header 286 128
Port 3 Cpl Data 1444 64