AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

3.11.1.2. Signal Tap Logic Analyzer

Using the Signal Tap Logic Analyzer, you can monitor the following top-level signals from the AXI Streaming Intel® FPGA IP for PCI Express* to confirm the failure symptom for any port type (Root Port, Endpoint) and configuration (Gen5/Gen4/Gen3).

Table 23.  Top-Level Signals to be Monitored for Debugging
Signal Description Expected value for successful link up
p<n>_pin_perst_n where n = 0, 1 Active-low asynchronous output signal from the PCIe* IP. It is derived from the pin_perst_n input signal. 1'b1
ninit_done Active-low asynchronous output signal from the Reset Release Intel FPGA IP. High indicates that the FPGA device is not yet fully configured, and low indicates the device has been configured and is in normal operating mode. For more details on the Reset Release Intel FPGA IP. 1'b0
p<n>_reset_status_n where n = 0, 1 Active-low output signal from the IP, synchronous to coreclkout_hip_toapp of the IP. The reset_status_n output of HIP drives this signal. Held low until pin_perst_n is deasserted and the PCIe Hard IP comes out of reset. When port bifurcation is used, there is one such signal for each port. The application logic can use this signal to drive its reset network. 1’b1
p<n>_ss_app_linkup where n = 0,1 Indicates the Physical link layer is up. Synchronous to coreclkout_hip_toapp clock of the IP. 1'b1
p<n>_ss_app_dlup where n = 0, 1 Indicates the data link layer is up. Synchronous to coreclkout_hip_toapp clock of the IP. 1’b1
p<n>_ss_app_ltssmstate[5:0] where n = 0, 1 (F/R-Tile) Indicates the LTSSM state, synchronous to coreclkout_hip of the Hard IP. Refer to the description for ltssm_state_o[5:0] below for the encodings of these state signals. 6’b11 (L0)
p<n>_ss_app_serr where n = 0, 1

Indicates system error is detected. Synchronous to coreclkout_hip_toapp clock of the IP.

EP mode: Asserted when the P-Tile PCIe Hard IP sends a message of correctable/non-fatal/fatal error.

1’b0
link_up_o Active-high output signal from the PCIe Hard IP, synchronous to coreclkout_hip clock of the HardIP. Indicates that the Physical Layer link is up. (This signal is currently available at the Hard IP interface). 1’b1
dl_up_o Active-high output signal from the PCIe Hard IP, synchronous to coreclkout_hip of the Hard IP. Indicates that the Data Link Layer is active. 1’b1

ltssm_state_o[5:0] (P-Tile)

Indicates the LTSSM state, synchronous to coreclkout_hip of the Hard IP. (This signal is currently available at the Hard IP interface)

  • 6'h00: S_DETECT_QUIET
  • 6'h01: S_DETECT_ACT
  • 6'h02: S_POLL_ACTIVE
  • 6'h03: S_POLL_COMPLIANCE
  • 6'h04: S_POLL_CONFIG
  • 6'h05: S_PRE_DETECT_QUIET
  • 6'h06: S_DETECT_WAIT
  • 6'h07: S_CFG_LINKWD_START
  • 6'h08: S_CFG_LINKWD_ACCEPT
  • 6'h09: S_CFG_LANENUM_WAIT
  • 6'h0A: S_CFG_LANENUM_ACCEPT
  • 6'h0B: S_CFG_COMPLETE
  • 6'h0C: S_CFG_IDLE
  • 6'h0D: S_RCVRY_LOCK
  • 6'h0E: S_RCVRY_SPEED
  • 6'h0F: S_RCVRY_RCVRCFG
  • 6'h10: S_RCVRY_IDLE
  • 6'h11: S_L0
  • 6'h12: S_L0S
  • 6'h13: S_L123_SEND_EIDLE
  • 6'h14: S_L1_IDLE
  • 6'h15: S_L2_IDLE
  • 6'h16: S_L2_WAKE
  • 6'h17: S_DISABLED_ENTRY
  • 6'h18: S_DISABLED_IDLE
  • 6'h19: S_DISABLED
  • 6'h1A: S_LPBK_ENTRY
  • 6'h1B: S_LPBK_ACTIVE
  • 6'h1C: S_LPBK_EXIT
  • 6'h1D: S_LPBK_EXIT_TIMEOUT
  • 6'h1E: S_HOT_RESET_ENTRY
  • 6'h1F: S_HOT_RESET
  • 6'h20: S_RCVRY_EQ0
  • 6'h21: S_RCVRY_EQ1
  • 6'h22: S_RCVRY_EQ2
  • 6'h23: S_RCVRY_EQ3
6’b11 (L0)
p<n>_ss_app_surprise_down_err where n=0,1 Active high asynchronous output signal. Indicates that a surprise down event is occurring in the HardIP controller. This error event is triggered when the PHY layer reports to the Data Link Layer that the link is down. 1’b0
p<n>_ss_app_rx_par_err where n=0,1 Indicates a parity error detected at the input of the HIP’S RX buffer. Asserts for a single cycle. Synchronous to the axi_st_clk clock.
Note: Application must reset the HardIP if this occurs because parity errors can leave the Hard IP in an unknown state.
1’b0
p<n>_ss_app_tx_par_err where n=0,1 Indicates a parity error during TX TLP transmission at the HIP. Asserts for a single cycle. Synchronous to the axi_st_clk clock. 1’b0