AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

4.19. AXI-Streaming Interface

The IP uses an AXI4 Streaming interface for transporting header and data information to and from the application logic. The header and data are presented as separate interfaces. The PCIe header, PF Number, VF Number, BAR number and Prefix information are grouped as a 32-byte header on the AXI Streaming interface.

The data is presented as 128-, 64- or 32-bytes wide bus, segmented into a number of segments depending on the configuration (Gen5/4/3 x8/x16) and mode used. The following modes are supported by the IP:
  • HIP Native mode (only for R-Tile)
  • Non-HIP Native mode
    • Simple packing mode
    • Compact packing mode

The HIP Native mode packing scheme is only available when you choose R-Tile. In this packing scheme, the AXI-ST Transmit and Receive interfaces follow all the rules that the AVST interface of the Native Hard IP follows for packing TLPs.

A packet must start from segment0 for a new cycle even for the compact packing mode. This constrains the design to send one packet per cycle. This is applicable to P/F/R-Tiles. Note that the HIP Native mode is not applicable to P/F-Tiles.
Note: The simple packing mode is not supported in the current Quartus® Prime release.

The compact packing scheme allows the header to be available in fixed locations. This is applicable to P/F/R-Tiles.

Refer to Application Packet Interface for details on how the application user logic must handle this interface in each of the configurations and modes.