AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.5. Configuration Intercept Interface

The IP allows application logic to intercept configuration read and configuration write requests using this interface. The interface follows AXI Streaming interface protocol with ready valid handshake. The interface will support a maximum of one outstanding request at a time. The IP provides st_ciireq and st_ciiresp interfaces for intercepting packets.

Note:
  1. This interface is provided so that the PCIe* IP is backward compatible to legacy application logic that relies on CII for their functionality. Newly defined application logic should avoid using the CII interface and move to the CEB interface.
  2. This interface is mutually exclusive with the Configuration Extension Bus Request Interface.

This interface is applicable only when operating in Endpoint mode.