AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.1.7. CFG REG IA CTRL

The following table lists details of configuration register indirect access control register.

Default Value: 0x0000_0000

Table 78.  Configuration Register Indirect Access Control
Register Name Bit Attribute User Side Description
CFG REG IA CTRL 0 RW

Initiate Access

This bit should be set when a master-like interface wants to read from or write to PCIe configuration space register.

The IP performs read or write operation to a function pointed to by IA_FN_NUM register when this bit is set and clears this bit indicating requested operation is complete.

Master cannot initiate new transaction if this bit is set.

1 RW

Access Type

Indicates access type of operation.

0 - Read Operation

1 - Write Operation

5-2 RW

Byte Enables

Indicates Byte Enables of Write Operations.

4'b0001: Write byte 0

4'b0010: Write byte 1

4'b0100: Write byte 2

4'b1000: Write byte 3

4'b1111: Write all bytes.

Any Combinations of byte enables are valid, e.g., 1010, 1011 etc.

15-6 RW

Register Address

DWORD Address of Register

31-16 RsvdZ Reserved