AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.1.5. POWER MANAGEMENT CTRL

Default Value: 0x0000_0000

Table 76.  Power Management Control Register
Register Name Bit Attribute User Side Description
POWER MANAGEMENT CTRL 0 RW

Generate PME Message

Wake Up. If PME is enabled and PME support is configured for current PMCSR D-state asserting this signal will cause the controller to wake from either L1 or L2 state. When the controller has transitioned back to the L0 state it will transmit a PME message and set the PME_Status.

Upon receiving the PME message the root complex should clear the PME_Status and change the D-state back to D0.

The IP passes on this information to HIP block and clears this bit indicating requested operation complete.

1 RW

Generate PME Turnoff Message

Only Available in RC Mode

The IP passes on this information to HIP block and clears this bit indicating requested operation complete.

Note: This is not applicable for Root Port Mode.
2 RW

Delay PM_Enter_L23 response

Indication from application that it is ready to enter the L23 state. The controller sends PM_Enter_L23 in response to PM_Turn_Off when this bit is set.

Application that do not require this feature hardware initialize bit[3].

If bit[3] is set this bit is do not care from hardware point of view.

The IP passes on this information to HIP block and clears this bit indicating requested operation complete.

3 Hwinit

Autonomous PM_Enter_L23 response

The controller sends PM_Enter_L23 in response to PM_Turn_Off.

When enabled, the HIP user input is tied to 1.

Note: This is not applicable for Root Port Mode.
15-4 RsvdZ Reserved
20-16 RW

PF Number

Indicates PF Number of Function generating PME.

Note: Current Quartus release limits to max 8 PFs only.
31-21 RsvdZ Reserved