GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

4.4.1. Connect the TX MAC Avalon Streaming Client Interface

Connect the TX MAC Avalon Streaming Client Interface of the GTS Ethernet Intel® FPGA Hard IP to a source that is compliant to the Avalon® Streaming Interface protocol.

Use the diagram below as an example of how to drive the TX MAC Avalon Streaming Client Interface to create and transmit an Ethernet frame.

Figure 29. Transmitting Data Using the TX MAC Avalon Streaming Client Interface
  • Hold i_tx_valid high from the start to end of a packet, and must be low outside of a packet.
  • Drive i_tx_startofpacket high on the first clock cycle of the frame transfer. Always start the packet on the MSB of the byte of i_tx_data, ensuring SOP aligned.
  • Hold the value on i_tx_data when o_tx_ready is deasserted. In this example, the Ready latency is configured to 1, therefore hold i_tx_data for 1 cycle after o_tx_ready is deasserted.
  • Drive i_tx_empty with the number of unused bytes in i_tx_data bus in the last clock cycle, coincident with i_tx_endofpacket, starting from the LSB (byte 0).
    • In this example, i_tx_data on the last cycle of the packet has 3 empty bytes.
    • The minimum number of valid bytes on the last cycle is 1.

You must drive the individual Avalon® Streaming Interface TX signals as described in the table below.

Table 25.  Signals of the TX MAC Avalon Streaming Client InterfaceAll interface signals are clocked by the TX clock. The signal names are standard TX MAC Avalon Streaming Client Interface signals with slight differences to indicate the variations.
Signal Name Width Description
Input Signals
i_tx_data[63:0] 64 bits

Input data (Ethernet Frame. Required content depends on the features enabled during IP configuration) to the MAC when the rate is 10GE/25GE. Bit 0 is the Least Significant Byte (LSB).

i_tx_valid 1 bit

Drive this signal high (HI) to qualify all input signals and buses in this table. This signal must be continuously asserted between the assertions of the start of packet and end of packet signals for the same packet.

i_tx_startofpacket 1 bit

Start of Packet (SOP)

When asserted, indicates that the TX data holds the first clock cycle of data in a packet (start of packet). Assert for only a single clock cycle for each packet. When the SOP signal is asserted, the MSB of the TX data drives the start of packet.

i_tx_endofpacket 1 bit

End of Packet (EOP)

When asserted, indicates that the TX data holds the final clock cycle of data in a packet (end of packet). Assert for only a single clock cycle for each packet.

For some legitimate packets, the SOP and EOP signals are asserted on the same clock cycle.

i_tx_empty[2:0] 3 bits

Indicates the number of empty bytes on the TX data when the EOP signal is asserted.

i_tx_error 1 bit

When asserted in an EOP cycle (while the EOP signal is asserted), directs the IP core to insert an error in the packet before sending it on the Ethernet link.

i_tx_skip_crc 1 bit

Drive this signal high for the duration of the frame transfer to disable CRC bytes and source address insertion by the IP core for the current frame. This means you provide the source address and CRC bytes.

If this signal is asserted, directs the TX MAC to not insert CRC, not add padding bytes, and not implement source address insertion.

If this signal is not asserted, and source address insertion is enabled, the TX MAC performs the following:
  • Overwrites the source address field with the value programmed in the TXMAC_SADDR register.
  • If necessary, the TX MAC inserts padding bytes and a CRC in the packet.
Output Signals
o_tx_ready 1 bit

Indicates that the IP is ready to accept data. If o_tx_ready is removed, then the i_tx_valid must also be removed after the configured ready latency settings in the IP GUI.