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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
The following figure shows the composition of an Ethernet Frame. Be aware of this while you make connections to the TX MAC Avalon Streaming Client Interface.
Figure 30. Fields and Frame Boundaries in an Ethernet Packet
When Preamble Passthrough is turned off, do not drive the Preamble of the Ethernet frame on the i_tx_data bus. Drive the first clock cycle with the destination address, as shown in the table below.
i_tx_clk (Cycle) | i_tx_data | Ethernet Frame Field | Description |
---|---|---|---|
1-> D0 | [63:56]' | Dest Addr[47:40] | The first octet of the Destination Address, follows Start Frame Delimiter (SFD). |
[55:48]' | Dest Addr[39:32] | - | |
[47:40]' | Dest Addr[31:24] | - | |
[39:32]' | Dest Addr[23:16] | - | |
[31:24]' | Dest Addr[15:8] | - | |
[23:16]' | Dest Addr[7:0] | - | |
[15:8]' | Src Addr[47:40] | When you turn on Source Address Insertion, content is replaced by the source address that is configured in the txmac_saddr register unless i_tx_skip_crc is high. | |
[7:0]' | Src Addr[39:32] | ||
2->D1 | [63:56] | Src Addr[31:24] | |
[55:48] | Src Addr[23:16] | ||
[47:40] | Src Addr[15:8] | ||
[39:32] | Src Addr[7:0] | ||
[31:24] | Length/Type[15:8] | - | |
[23:16] | Length/Type[7:0] | - | |
[15:0] | … | - |
Note: The byte order flows from left to right on the bus – the first byte of the MAC destination address is the leftmost byte; the MAC treats this as the first byte after the Start Frame Delimiter (SFD). The bit numbered 0 in the Ethernet Specification is the rightmost bit of each byte.