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Visible to Intel only — GUID: fzg1697543969248
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4.4.2. Connect the RX MAC Avalon Streaming Client Interface
Connect the RX MAC Avalon Streaming Client Interface of the GTS Ethernet Intel® FPGA Hard IP to a sink component that is compatible with the Avalon Streaming Client Interface protocol.
You must sample and process the individual Avalon Streaming RX signals according to the description provided in the table below.
The following figure shows how to receive data using the RX MAC Avalon Streaming client interface. The interface complies with the Avalon® Streaming Interface specification.
You must sample and process each individual Avalon Streaming RX signal according to the descriptions provided in the table below.
Signal Name | Width | Description |
---|---|---|
o_rx_data[63:0] | 64 bits | Output data (Ethernet Frame. Required content depends on the features enabled during IP configuration) from the MAC when the rate is 10 GE/25 GE. Bit 0 is the Least Significant Byte (LSB). |
o_rx_valid | 1 bit | You must sample o_rx_data and the other RX MAC Avalon Streaming signals when the signal is asserted. |
o_rx_empty[2:0] | 3 bits | Indicates the number of empty bytes on the RX data signal when EOP signal is asserted, starting from the (LSB). |
o_rx_startofpacket | 1 bit | When asserted, indicates that the RX data signal holds the first clock cycle of data in a packet (start of packet). The IP core asserts this signal for only a single clock cycle for each packet. When the SOP signal is asserted, the MSB of the RX data signal drives the start of packet. |
o_rx_endofpacket | 1 bit | When asserted, indicates that the RX data signal holds the final clock cycle of data in a packet (end of packet). The IP core asserts this signal for only a single clock cycle for each packet. In the case of an undersized frame or in the case of a frame that is exactly 64 bytes long, the SOP and EOP signals are asserted in the same clock cycle. |
o_rx_error[5:0] | 6 bits | Sample this bus to identify if the current packet has errors.
The individual bits report different types of errors:
|
o_rxstatus_data[39:0] | 40 bits | Sample this bus to process status information about the current packet. Sample with o_rx_endofpacket.
|
o_rxstatus_valid | 1 bit | When asserted, indicates that o_rxstatus_data is driving valid data. |
Section Content
Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
Receive Ethernet Frame with Preamble Passthrough Enabled
Receive Ethernet Frame with Remove CRC bytes Disabled
Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface