GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

4.4.2. Connect the RX MAC Avalon Streaming Client Interface

Connect the RX MAC Avalon Streaming Client Interface of the GTS Ethernet Intel® FPGA Hard IP to a sink component that is compatible with the Avalon Streaming Client Interface protocol.

You must sample and process the individual Avalon Streaming RX signals according to the description provided in the table below.

The following figure shows how to receive data using the RX MAC Avalon Streaming client interface. The interface complies with the Avalon® Streaming Interface specification.

Figure 33. Receiving Data Using the RX MAC Avalon Streaming Client Interface

Packets always start on the most significant bit of o_rx_data (SOP aligned).

  • When the frame ends, o_rx_empty is set to the number of unused bytes in o_rx_data, starting from the LSB (byte 0).
  • In this example, o_rx_data on the last cycle of the packet has 5 empty bytes.
  • The last clock cycle can contain a minimum of 1 byte.
  • The framing and data ports are only valid when o_rx_valid is high.

The interface does not support direct back pressure. Your client application, Avalon Streaming Sink, must be able to process all received frames at the supported data rate.

You must sample and process each individual Avalon Streaming RX signal according to the descriptions provided in the table below.

Table 29.  Signals of the RX MAC Avalon Streaming Client InterfaceThe i_clk_rx clocks all interface signals. The signal names are standard Avalon Streaming Interface signals with slight differences to indicate the variations.
Signal Name Width Description
o_rx_data[63:0] 64 bits Output data (Ethernet Frame. Required content depends on the features enabled during IP configuration) from the MAC when the rate is 10 GE/25 GE. Bit 0 is the Least Significant Byte (LSB).
o_rx_valid 1 bit

You must sample o_rx_data and the other RX MAC Avalon Streaming signals when the signal is asserted.

o_rx_empty[2:0] 3 bits Indicates the number of empty bytes on the RX data signal when EOP signal is asserted, starting from the (LSB).
o_rx_startofpacket 1 bit

When asserted, indicates that the RX data signal holds the first clock cycle of data in a packet (start of packet). The IP core asserts this signal for only a single clock cycle for each packet.

When the SOP signal is asserted, the MSB of the RX data signal drives the start of packet.

o_rx_endofpacket 1 bit

When asserted, indicates that the RX data signal holds the final clock cycle of data in a packet (end of packet). The IP core asserts this signal for only a single clock cycle for each packet.

In the case of an undersized frame or in the case of a frame that is exactly 64 bytes long, the SOP and EOP signals are asserted in the same clock cycle.

o_rx_error[5:0] 6 bits

Sample this bus to identify if the current packet has errors.

The individual bits report different types of errors:
  • Bit [0]: Malformed packet error. If this bit has the value of 1, the packet is malformed. The IP core identifies a malformed packet when it receives a control character that is not a terminate character.
  • Bit [1]: CRC error. If this bit has the value of 1, the IP core detected a CRC error, error character in the frame, malformed, undersized, or truncated packets.
  • Bit [2]: Undersized or Oversized frame. The IP core does not recognize an incoming frame of size eight bytes or less as a frame, and those cases are not reported here. If the preamble- passthrough and CRC forwarding settings cause the RX MAC to strip out bytes such that only eight bytes or less remain in the frame, the IP core also does not recognize the frame, and those cases are not reported here. If the frame is malformed, the case is not reported here.
  • Bit [3]: Reserved.
  • Bit [4]: payload length error. If this bit has the value of 1, the payload received in the frame is shorter than the length field value, and the value in the length field is less than or equal 1500 bytes. If the frame is oversized or undersized, the case is not reported here. If the frame is malformed, the case is not reported here.
  • Bit [5]: Reserved. Tied to 0.
o_rxstatus_data[39:0] 40 bits

Sample this bus to process status information about the current packet. Sample with o_rx_endofpacket.

  • [0:32]: Reserved
  • [33]: When asserted, indicates a VLAN/stacked VLAN(SVLAN) frame
  • [34]: When asserted, indicates a control frame(includes PAUSE/PFC)
  • [35]: When asserted, indicates a PAUSE/PFC frame
  • [36]: Reserved
  • [37]: When asserted, indicates a Broadcast/Multicast frame
  • [38: 39]: Reserved

    When more than one status is valid at the same time, the outputs are based on the priority.

    The order of priority should be: VLAN/SVLAN frame > PAUSE/PFC frame > control frame > Broadcast/Multicast frame, with the exception that PAUSE/PFC can also be indicated as control, i.e., bit [34].

o_rxstatus_valid 1 bit When asserted, indicates that o_rxstatus_data is driving valid data.