GTS Ethernet Intel® FPGA Hard IP User Guide

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ID 817676
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Install and License the GTS Ethernet Intel® FPGA Hard IP 3. Configure and Generate Ethernet Hard IP variant 4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application 5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance 6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance 7. Simulate, Compile, and Validate SyncE - Single Instance 8. Simulate and Compile PTP1588 - Single Instance 9. Simulate, Compile, and Validate - Multiple Instance 10. Troubleshoot and Diagnose Issues A. Appendix A: Functional Description B. Appendix B: Configuration Registers C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Release Information 1.2. High-Level Functional Overview 1.3. Acronyms 1.4. Agilex™ 5 Ethernet Portfolio and Target Applications 1.5. Agilex™ 5 Ethernet Hard IP Features 1.6. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.5. Agilex™ 5 Ethernet Hard IP Features x
1.5.1. Device Family Support 1.5.2. Device Speed Grade Support 1.5.3. Resource Utilization
3. Configure and Generate Ethernet Hard IP variant x
3.1. Create Quartus Project 3.2. Configure GTS Ethernet Hard IP 3.3. Generate HDL for Synthesis and Simulation 3.4. Generated File Structure 3.5. Generate GTS EHIP Design Example 3.6. Analog Parameter Options
3.5. Generate GTS EHIP Design Example x
3.5.1. Directory Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application x
4.1. Implement Required Clocking 4.2. Implement Required Resets 4.3. Connect the Status Interface 4.4. Connect the MAC Avalon Streaming Client Interface 4.5. Connect the MII PCS Only Client Interface 4.6. Connect the PCS66 Client Interface – FlexE and OTN 4.7. Connect the Precision Time Protocol Interface 4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.1. Implement Required Clocking x
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance 4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances 4.1.3. Implement Clock Connections to MAC Asynchronous Operation 4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.5. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets x
4.2.1. Reset Sequence 4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP
4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP x
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. Connect the Status Interface x
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface x
4.4.1. Connect the TX MAC Avalon Streaming Client Interface 4.4.2. Connect the RX MAC Avalon Streaming Client Interface 4.4.3. Connect the MAC Flow Control Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface x
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion 4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface x
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled 4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled 4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled 4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface x
4.4.3.1. Connect the TX MAC Flow Control Interface 4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface x
4.5.1. Connect the MII PCS Mode TX Interface 4.5.2. Connect the MII PCS Mode RX Interface
4.5.1. Connect the MII PCS Mode TX Interface x
4.5.1.1. Insert Alignment Marker
4.5.2. Connect the MII PCS Mode RX Interface x
4.5.2.1. Receive Alignment Marker
4.6. Connect the PCS66 Client Interface – FlexE and OTN x
4.6.1. Connect the FlexE and OTN Mode TX Interface 4.6.2. Connect the FlexE and OTN Mode RX Interface
4.6.1. Connect the FlexE and OTN Mode TX Interface x
4.6.1.1. Insert Alignment Marker
4.6.2. Connect the FlexE and OTN Mode RX Interface x
4.6.2.1. Receive Alignment Marker
4.7. Connect the Precision Time Protocol Interface x
4.7.1. Connect the Time-of-Day Interface 4.7.2. Connect the TX Two-Step Timestamp Interface 4.7.3. Connect the TX One-Step Timestamp Interface 4.7.4. Connect the RX Timestamp Interface 4.7.5. Connect the PTP Status Interface
4.7.3. Connect the TX One-Step Timestamp Interface x
4.7.3.1. PTP Field Offset for 1-Step Operation
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance x
5.1. Design Example Features 5.2. Design Example Components 5.3. Simulate the Design Example 5.4. Compile the Design Example in Hardware 5.5. Validate the Design Example in Hardware
5.3. Simulate the Design Example x
5.3.1. Simulation Testbench Flow 5.3.2. Verify the Simulation Results
5.5. Validate the Design Example in Hardware x
5.5.1. Configure the Clocks in Hardware 5.5.2. Program the FPGA 5.5.3. Run the Hardware Test
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance x
6.1. Design Example Features 6.2. Design Example Components 6.3. Simulate the Design Example 6.4. Compile the Design Example in Hardware 6.5. Validate the Design Example in Hardware
6.3. Simulate the Design Example x
6.3.1. Simulation Testbench Flow 6.3.2. Simulators Output
6.5. Validate the Design Example in Hardware x
6.5.1. Configure the Clocks in Hardware 6.5.2. Program the FPGA 6.5.3. Run the Hardware Test
7. Simulate, Compile, and Validate SyncE - Single Instance x
7.1. Design Example Features 7.2. Design Example Components 7.3. Simulate the Design Example 7.4. Compile the Design Example in Hardware 7.5. Validate the Design Example in Hardware
7.3. Simulate the Design Example x
7.3.1. Simulation Testbench Flow for Single Instance with SyncE 7.3.2. Simulator Output
7.5. Validate the Design Example in Hardware x
7.5.1. Configure the Clocks in Hardware 7.5.2. Program the FPGA 7.5.3. Run the Hardware Test
8. Simulate and Compile PTP1588 - Single Instance x
8.1. Design Example Features 8.2. Design Example Components 8.3. Simulate the Design Example 8.4. Compile the Design Example in Hardware
8.3. Simulate the Design Example x
8.3.1. Simulation Testbench Flow 8.3.2. Simulator Output
9. Simulate, Compile, and Validate - Multiple Instance x
9.1. Design Example Features 9.2. Design Example Components 9.3. Simulate the Design Example 9.4. Compile the Design Example in Hardware 9.5. Validate the Design Example in Hardware
9.3. Simulate the Design Example x
9.3.1. Simulation Testbench Flow for MAC Mode 9.3.2. Simulator Output
9.5. Validate the Design Example in Hardware x
9.5.1. Configure the Clocks in Hardware 9.5.2. Program the FPGA 9.5.3. Run the Hardware Test
10. Troubleshoot and Diagnose Issues x
10.1. Enable Diagnostic Lookback Modes 10.2. Troubleshoot the Reset Sequence 10.3. Use Signal Tap Analyzer for Troubleshooting
10.1. Enable Diagnostic Lookback Modes x
10.1.1. Internal Serial Loopback 10.1.2. Enable MAC Loopback 10.1.3. Enable PCS Loopback 10.1.4. Enable External Loopback 10.1.5. Packet Client Loopback
10.2. Troubleshoot the Reset Sequence x
10.2.1. Debug the Power Up Reset Sequence 10.2.2. Debug the TX Reset Entry Sequence 10.2.3. Debug the TX Reset Exit Sequence 10.2.4. Debug the RX Reset Entry Sequence 10.2.5. Debug the RX Reset Exit Sequence 10.2.6. Debug the Auto Recovery Reset Sequence
A. Appendix A: Functional Description x
A.1. Datapath Description A.2. GTS Ethernet Intel® FPGA Hard IP MAC A.3. PCS, OTN, and FlexE Modes A.4. Precision Time Protocol Interface
A.2. GTS Ethernet Intel® FPGA Hard IP MAC x
A.2.1. MAC TX Datapath A.2.2. MAC RX Datapath A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) A.2.4. Link Fault Signaling A.2.5. Order of Ethernet Transmission:
A.2.1. MAC TX Datapath x
A.2.1.1. Insert TX Preamble, Start, and SFD A.2.1.2. Insert Source Address A.2.1.3. Process Length/Type Field A.2.1.4. Pad the Client Frame A.2.1.5. Insert Frame Check Sequence (CRC-32) A.2.1.6. Generate and Insert Inter-Packet Gap
A.2.2. MAC RX Datapath x
A.2.2.1. Process RX Preamble A.2.2.2. Check RX Strict SFD A.2.2.3. Check RX FCS A.2.2.4. Handle RX Malformed Packet A.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames A.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors A.2.2.7. Inter-Packet Gap
A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
A.2.3.1. Conditions Triggering XOFF Frame Transmission A.2.3.2. Conditions Triggering XON Frame Transmission A.2.3.3. Pause Control and Generation Interface A.2.3.4. Pause Control Frame Filtering
A.3. PCS, OTN, and FlexE Modes x
A.3.1. PCS Mode A.3.2. OTN Mode A.3.3. FlexE Mode
A.4. Precision Time Protocol Interface x
A.4.1. Features A.4.2. PTP User Flow A.4.3. Make PTP UI Adjustments A.4.4. Reference Time Interval A.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
A.4.2. PTP User Flow x
A.4.2.1. PTP TX User Flow A.4.2.2. PTP RX User Flow
A.4.3. Make PTP UI Adjustments x
A.4.3.1. Adjust TX UI A.4.3.2. Adjust RX UI
B. Appendix B: Configuration Registers x
B.1. Ethernet Avalon® Memory-Mapped Interface Address Space B.2. Packet Client Registers
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide

4.4.2. Connect the RX MAC Avalon Streaming Client Interface

Connect the RX MAC Avalon Streaming Client Interface of the GTS Ethernet Intel® FPGA Hard IP to a sink component that is compatible with the Avalon Streaming Client Interface protocol.

You must sample and process the individual Avalon Streaming RX signals according to the description provided in the table below.

The following figure shows how to receive data using the RX MAC Avalon Streaming client interface. The interface complies with the Avalon® Streaming Interface specification.

Figure 33. Receiving Data Using the RX MAC Avalon Streaming Client Interface

Packets always start on the most significant bit of o_rx_data (SOP aligned).

  • When the frame ends, o_rx_empty is set to the number of unused bytes in o_rx_data, starting from the LSB (byte 0).
  • In this example, o_rx_data on the last cycle of the packet has 5 empty bytes.
  • The last clock cycle can contain a minimum of 1 byte.
  • The framing and data ports are only valid when o_rx_valid is high.

The interface does not support direct back pressure. Your client application, Avalon Streaming Sink, must be able to process all received frames at the supported data rate.

You must sample and process each individual Avalon Streaming RX signal according to the descriptions provided in the table below.

Table 29.  Signals of the RX MAC Avalon Streaming Client InterfaceThe i_clk_rx clocks all interface signals. The signal names are standard Avalon Streaming Interface signals with slight differences to indicate the variations.
Signal Name Width Description
o_rx_data[63:0] 64 bits Output data (Ethernet Frame. Required content depends on the features enabled during IP configuration) from the MAC when the rate is 10 GE/25 GE. Bit 0 is the Least Significant Byte (LSB).
o_rx_valid 1 bit

You must sample o_rx_data and the other RX MAC Avalon Streaming signals when the signal is asserted.

o_rx_empty[2:0] 3 bits Indicates the number of empty bytes on the RX data signal when EOP signal is asserted, starting from the (LSB).
o_rx_startofpacket 1 bit

When asserted, indicates that the RX data signal holds the first clock cycle of data in a packet (start of packet). The IP core asserts this signal for only a single clock cycle for each packet.

When the SOP signal is asserted, the MSB of the RX data signal drives the start of packet.
o_rx_endofpacket 1 bit

When asserted, indicates that the RX data signal holds the final clock cycle of data in a packet (end of packet). The IP core asserts this signal for only a single clock cycle for each packet.

In the case of an undersized frame or in the case of a frame that is exactly 64 bytes long, the SOP and EOP signals are asserted in the same clock cycle.

o_rx_error[5:0] 6 bits

Sample this bus to identify if the current packet has errors.

The individual bits report different types of errors:
  • Bit [0]: Malformed packet error. If this bit has the value of 1, the packet is malformed. The IP core identifies a malformed packet when it receives a control character that is not a terminate character.
  • Bit [1]: CRC error. If this bit has the value of 1, the IP core detected a CRC error, error character in the frame, malformed, undersized, or truncated packets.
  • Bit [2]: Undersized or Oversized frame. The IP core does not recognize an incoming frame of size eight bytes or less as a frame, and those cases are not reported here. If the preamble- passthrough and CRC forwarding settings cause the RX MAC to strip out bytes such that only eight bytes or less remain in the frame, the IP core also does not recognize the frame, and those cases are not reported here. If the frame is malformed, the case is not reported here.
  • Bit [3]: Reserved.
  • Bit [4]: payload length error. If this bit has the value of 1, the payload received in the frame is shorter than the length field value, and the value in the length field is less than or equal 1500 bytes. If the frame is oversized or undersized, the case is not reported here. If the frame is malformed, the case is not reported here.
  • Bit [5]: Reserved. Tied to 0.
o_rxstatus_data[39:0] 40 bits

Sample this bus to process status information about the current packet. Sample with o_rx_endofpacket.

  • [0:32]: Reserved
  • [33]: When asserted, indicates a VLAN/stacked VLAN(SVLAN) frame
  • [34]: When asserted, indicates a control frame(includes PAUSE/PFC)
  • [35]: When asserted, indicates a PAUSE/PFC frame
  • [36]: Reserved
  • [37]: When asserted, indicates a Broadcast/Multicast frame
  • [38: 39]: Reserved

    When more than one status is valid at the same time, the outputs are based on the priority.

    The order of priority should be: VLAN/SVLAN frame > PAUSE/PFC frame > control frame > Broadcast/Multicast frame, with the exception that PAUSE/PFC can also be indicated as control, i.e., bit [34].

o_rxstatus_valid 1 bit When asserted, indicates that o_rxstatus_data is driving valid data.

Section Content
Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
Receive Ethernet Frame with Preamble Passthrough Enabled
Receive Ethernet Frame with Remove CRC bytes Disabled
Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface

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