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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
Sample the Ethernet Frame Destination Address on the first clock cycle of the RX MAC Avalon Streaming Client Interface when the Preamble Disabled is turned off. Refer to the table below for details.
i_clk_rx(cycle) | o_rx_data | MAC Field | Description |
---|---|---|---|
1->D0 | [63:56] | Dest Addr[47:40] | The first octet of the Destination Address, follows Start Frame Delimiter (SFD). |
[55:48] | Dest Addr[39:32] | - | |
[47:40] | Dest Addr[31:24] | - | |
[39:32] | Dest Addr[23:16] | - | |
[31:24] | Dest Addr[15:8] | - | |
[23:16] | Dest Addr[7:0] | - | |
[15:8] | Src Addr[47:40] | - | |
2->D1 | [7:0] | Src Addr[39:32] | - |
[63:56] | Src Addr[31:24] | - | |
[55:48] | Src Addr[23:16] | - | |
[47:40] | Src Addr[15:8] | - | |
[39:32] | Src Addr[7:0] | - | |
[31:24] | Length/Type[15:8] | - | |
[23:16] | Length/Type[7:0] | - | |
[15:0] | … | - |
The byte order of the data is the same as the TX MAC SOP-Aligned Client interface – the first byte of the packet received was the MSB of the bus.
- The bit order of the data also matches the TX MAC SOP-Aligned Client interface.
- For 10GE/25GE, the first bit of the first received byte is bit 56.
Note: The Ethernet header arrives over two clock cycles for the 10GE/25GE interfaces.