GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

10.3.1. Simulation Testbench Flow

The following steps show the simulation testbench flow:
  1. Assert global reset (i_rst_n) to reset each GTS Ethernet Intel® FPGA IP and GTS Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP.
  2. Wait until configuration settings load
  3. Wait until reset acknowledgment. The o_rst_ack_n signal goes low..
  4. Deasserts the global resets, i_rst_n and i_reconfig_rst.
  5. Wait until the auto-negotiation is complete, and then begin the data mode.
  6. Wait until link training is complete.
  7. Wait until o_tx_lanes_stable bit is set to 1, indicating TX path is ready.
  8. Wait until o_rx_pcs_ready bit is set to 1, indicating RX path is ready.
  9. Instruct packet client to transmit data. Write hw_pc_ctrl[0]=1'b1 to start the packet generator.
  10. Read TX packet data information from 0x20 - 0x34 registers. Read registers in a sequential order.
  11. Read RX packet data information from 0x38 - 0x4C registers. Read registers in a sequential order.
  12. Compare the counters to ensure 16 packets were sent and received.
  13. Instruct packet client to stop data transmission. Write hw_pc_ctrl[2:0]=3'b100 to stop the packet generator. Clear counters.
  14. Perform Avalon® memory-mapped interface test. Write and read Ethernet IP registers.
    • 0x104: Scratch register
    • 0x108: IP soft reset register
    • 0x014: Lower 32 bits of TX MAC Source address Register
    • 0x018: Upper 16 bits of TX MAC Source address Register
    • 0x01C: Max RX frame size register
  15. Perform Avalon® memory-mapped interface 2 test to read and write operation transceiver registers.