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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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4.2.1. Reset Sequence
This section describes the reset sequence.
Figure 22. Reset Sequence
The following steps describe the IP core reset sequence as shown in the above waveform.
- Assert the i_rst_n signal, and then make sure that both i_tx_rst_n and i_rx_rst_n signals are already deasserted.
- The o_rst_ack_n reset signal deasserts. This indicates that the IP core is out of reset.
Note: The o_tx_rst_ack_n and o_rx_rst_ack_n reset signals are also deasserted.
- The IP core is fully out of reset. IP asserts o_tx_lanes_stable and o_rx_pcs_ready to indicate that the TX and RX data paths are ready for use.
- Assert the i_tx_rst_n reset signal.
- The o_tx_lanes_stable signal deasserts to indicate that the TX datapath is no longer operational.
- The o_tx_rst_ack_n signal asserts indicating that the TX datapath is fully in reset. Then, deassert the i_tx_rst_n signal to bring the TX datapath out of the reset.
- Assert the i_rx_rst_n reset signal.
- The o_rx_pcs_ready signal deasserts to indicate that the RX datapath is no longer operational.
- The o_rx_rst_ack_n signal asserts indicating that the RX datapath is fully in reset. Then, deassert the i_rx_rst_n signal to bring the RX datapath out of the reset.
- Assert the i_rst_n reset signal.
- The o_tx_lanes_stable and o_rx_pcs_ready signals deassert to indicate that TX and RX datapath are no longer operational.
- The o_rst_ack_n signals assert to indicate the IP core is fully in reset. To bring the IP core out of the reset, deassert the i_rst_n reset signal.