GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

A.3.1. PCS Mode

The GTS Ethernet Intel® FPGA Hard IP supports PCS only mode in 10GE/25GE Ethernet rate variants with optional FEC feature.

The TX PCS datapath consists of:

  • TX PCS encoder—encodes the data from the PMA interface.
  • TX PCS scrambler—enables the data to be scrambled. Channels does not lock correctly if the data is not scrambled.
  • Alignment insertion—the TX PCS interface inserts alignment markers.
  • Striper—enables logically sequential data to be segmented to increase data throughput.

The RX PCS datapath consists of:

  • Aligner—enables the alignment of incoming data.
  • RX PCS descrambler—enables the incoming scrambled data to be descrambled.
  • RX PCS decoder—decodes the incoming encoded data from the PMA interface.