GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

10.2. Design Example Components

Figure 68. The GTS Ethernet Intel® FPGA Hard IP Simulation Design Example Block Diagram
The GTS Ethernet Intel® FPGA Hard IP design example includes the following components:
Design Component Description
GTS Ethernet Intel® FPGA Hard IP Instantiates the GTS Ethernet Intel® FPGA Hard IP (intel_eth_gts) with any supported configuration as shown in Simulate, Compile, and Validate (MAC+PCS) - Single Instance.
Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP The GTS Ethernet Intel® FPGA Hard IP instantiates this IP when Enable auto-negotiation and link training is selected.
GTS System PLL Clocks Intel® FPGA Hard IP This IP provides the system clock i_clk_sys signal to the GTS Ethernet Intel® FPGA Hard IP .
GTS Reset Sequencer Intel® FPGA Hard IP This IP provides the PMA Control Unit clock i_pma_cu_clk to the GTS Ethernet Intel® FPGA Hard IP .
Packet Client Generates traffic pattern for MAC mode and non-MAC modes.
Avalon® memory-mapped interface Decoder Decodes the Avalon® memory-mapped interface address.