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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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4.4.3.2. Connect the RX MAC Flow Control Interface
All interface signals are clocked by the i_clk_tx clock. For 10GE/25GE channels, all interface signals are asynchronous.
Signal Name | Width (bits) | Description |
---|---|---|
o_rx_pause | 1 bit | When asserted, stop sending Ethernet frames on the TX MAC client interface since the IP core received a PAUSE XOFF frame. |
o_rx_pfc[7:0] | 8 bits | When a bit is asserted, stop sending Ethernet frames on the TX MAC client interface for the corresponding priority queue since the IP core received a PFC XOFF frame. |
The o_rx_pause and o_rx_pfc[7:0] ports on each channel are asserted when their remote link partner sets one or more of the queues to a non-zero pause quanta.
Figure 36. Example of o_rx_pause Toggling
In the above diagram, o_rx_pause is asserted because the remote link partner sends a PAUSE XOFF request. The quanta count from the PAUSE XOFF request remains high in o_rx_pause until it expires.
- When a PAUSE XOFF request is received and Stop TX traffic when link partner sends pause parameter is enabled in GUI, the TX MAC stops sending traffic.
- When a PAUSE XOFF request is received and Stop TX traffic when link partner sends pause parameter is disabled in the GUI, the TX MAC sends traffic. o_rx_pause deasserts on every valid cycle in the IP. The width of the pulse indicates the number of cycles of pause required.
Figure 37. Example of o_rx_pfc[7:0] Toggling
- For all channels, one quanta is worth multiple cycles of pause. Each quanta is worth 512 cycles.
- o_rx_pfc is asserted when the remote link partner sends a PFC XOFF request. In the diagram below, a PFC (Priority Flow Control) request is sent for queue[0], and then later for queue[6].
Note: The same PFC packet can set multiple queues. The PFC quanta counters count down on each valid cycle. Therefore, the pulse width shows the length of the traffic pause necessary for each queue. The PFC quanta values can be configured using PFC_Pause_quanta registers. Refer to the Agilex™ 5 Ethernet Intel® FPGA Hard IP Register Map for more information.