GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

4.5.1. Connect the MII PCS Mode TX Interface

The GTS Ethernet Intel® FPGA Hard IP TX client interface in PCS variations is Media Independent Interface (MII).

Connect the TX MII interface (which is a sink) to an MII compliant source. Connect the interface according to the table below.

Table 33.  MII TX Client Interface SignalsAll interface signals are clocked by the i_clk_tx The signal names are standard MII interface signals.
Signal Name Width Description
i_tx_mii_d[63:0] 64 bits (10GE/25GE) Drive MII encoded control bytes or Ethernet frame content on this input data bus.
  • i_tx_mii_d[7:0] holds the first byte the IP core transmits on the Ethernet link.
  • i_tx_mii_d[0] holds the first bit the IP core transmits on the Ethernet link.
i_tx_mii_c[7:0] 8 bits (10GE/25GE) For each control byte driven into i_tx_mii_d bus, drive the corresponding bit high. For example, i_tx_mii_c[0] corresponds to i_tx_mii_d[7:0].
  • If the value of a bit is 1, the corresponding data byte is a control byte.
  • If the value of a bit is 0, the corresponding data byte is data.
i_tx_mii_valid 1 bit Drive this signal high to qualify the data or control bytes on the i_tx_mii_d bus.
o_tx_mii_ready 1 bit When this signal is deasserted, stop driving valid data on the i_tx_mii_d bus since the IP core is not ready to receive. You must deassert i_tx_mii_valid within 6 clock cycles of this signal being deasserted. Refer Figure 38 for reference.
i_tx_mii_am 1 bit Alignment marker insertion bit (Applicable only for RS-FEC). Drive this signal to 0 if Firecode FEC or NO FEC is enabled.

Drive this signal to 0 if Firecode FEC or No FEC is enabled.

The following waveform shows how to send packets directly to the PCS TX interface.
Figure 38. Transmitting Data on the PCS Mode TX Interface
  • Drive i_tx_mii_valid according to the following rules:
    • Assert the i_tx_mii_valid only when the o_tx_mii_ready is asserted, and deassert only when the o_tx_mii_ready is deasserted.
    • Space the i_tx_mii_valid and o_tx_mii_ready signals by a fixed latency between one and six signals.
    • Hold the values of i_tx_mii_d and i_tx_mii_c when i_tx_mii_valid is low.
  • Bytes are transmitted from Least Significant Byte (LSB) to Most Significant Byte (MSB) order. The initial byte to be transferred from the interface is represented by the 8-bit value i_tx_mii_d[7:0].
  • The first bit to be transmitted is the LSB of that byte, which is i_tx_mii_d[0].
Note: The PCS TX interface is not SOP aligned. Any valid ordering of packets in MII format is accepted.
Transmit a start of packet and preamble with an SFD byte according to the table below.
Table 34.  Sending a Start Packet Block with Preamble to the PCS TX Interface
MII Data MII Control Ethernet Packet Byte
i_tx_mii_d[7:0] 0xFB i_tx_mii_c[0] 1 Start of Packet
i_tx_mii_d[15:8] 0x55 i_tx_mii_c[1] 0 Preamble
i_tx_mii_d[23:16] 0x55 i_tx_mii_c[2] 0 Preamble
i_tx_mii_d[31:24] 0x55 i_tx_mii_c[3] 0 Preamble
i_tx_mii_d[39:32] 0x55 i_tx_mii_c[4] 0 Preamble
i_tx_mii_d[47:40] 0x55 i_tx_mii_c[5] 0 Preamble
i_tx_mii_d[55:48] 0x55 i_tx_mii_c[6] 0 Preamble
i_tx_mii_d[63:56] 0xD5 i_tx_mii_c[7] 0 SFD