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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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4.5.1. Connect the MII PCS Mode TX Interface
The GTS Ethernet Intel® FPGA Hard IP TX client interface in PCS variations is Media Independent Interface (MII).
Connect the TX MII interface (which is a sink) to an MII compliant source. Connect the interface according to the table below.
Signal Name | Width | Description |
---|---|---|
i_tx_mii_d[63:0] | 64 bits (10GE/25GE) | Drive MII encoded control bytes or Ethernet frame content on this input data bus.
|
i_tx_mii_c[7:0] | 8 bits (10GE/25GE) | For each control byte driven into i_tx_mii_d bus, drive the corresponding bit high. For example, i_tx_mii_c[0] corresponds to i_tx_mii_d[7:0].
|
i_tx_mii_valid | 1 bit | Drive this signal high to qualify the data or control bytes on the i_tx_mii_d bus. |
o_tx_mii_ready | 1 bit | When this signal is deasserted, stop driving valid data on the i_tx_mii_d bus since the IP core is not ready to receive. You must deassert i_tx_mii_valid within 6 clock cycles of this signal being deasserted. Refer Figure 38 for reference. |
i_tx_mii_am | 1 bit | Alignment marker insertion bit (Applicable only for RS-FEC). Drive this signal to 0 if Firecode FEC or NO FEC is enabled. Drive this signal to 0 if Firecode FEC or No FEC is enabled. |
The following waveform shows how to send packets directly to the PCS TX interface.
Figure 38. Transmitting Data on the PCS Mode TX Interface
- Drive i_tx_mii_valid according to the following rules:
- Assert the i_tx_mii_valid only when the o_tx_mii_ready is asserted, and deassert only when the o_tx_mii_ready is deasserted.
- Space the i_tx_mii_valid and o_tx_mii_ready signals by a fixed latency between one and six signals.
- Hold the values of i_tx_mii_d and i_tx_mii_c when i_tx_mii_valid is low.
- Bytes are transmitted from Least Significant Byte (LSB) to Most Significant Byte (MSB) order. The initial byte to be transferred from the interface is represented by the 8-bit value i_tx_mii_d[7:0].
- The first bit to be transmitted is the LSB of that byte, which is i_tx_mii_d[0].
Note: The PCS TX interface is not SOP aligned. Any valid ordering of packets in MII format is accepted.
Transmit a start of packet and preamble with an SFD byte according to the table below.
MII Data | MII Control | Ethernet Packet Byte | ||
---|---|---|---|---|
i_tx_mii_d[7:0] | 0xFB | i_tx_mii_c[0] | 1 | Start of Packet |
i_tx_mii_d[15:8] | 0x55 | i_tx_mii_c[1] | 0 | Preamble |
i_tx_mii_d[23:16] | 0x55 | i_tx_mii_c[2] | 0 | Preamble |
i_tx_mii_d[31:24] | 0x55 | i_tx_mii_c[3] | 0 | Preamble |
i_tx_mii_d[39:32] | 0x55 | i_tx_mii_c[4] | 0 | Preamble |
i_tx_mii_d[47:40] | 0x55 | i_tx_mii_c[5] | 0 | Preamble |
i_tx_mii_d[55:48] | 0x55 | i_tx_mii_c[6] | 0 | Preamble |
i_tx_mii_d[63:56] | 0xD5 | i_tx_mii_c[7] | 0 | SFD |