Visible to Intel only — GUID: xyy1697543692054
Ixiasoft
Visible to Intel only — GUID: xyy1697543692054
Ixiasoft
4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP
Instantiate and connect the GTS Reset Sequencer Intel® FPGA IP to the GTS Ethernet Intel® FPGA Hard IP . The following subsections describe this process:
The GTS Reset Sequencer Intel® FPGA IP receives reset requests from the GTS Ethernet Intel® FPGA Hard IP and grants them based on priority.
Signal Name | Width | Description |
---|---|---|
i_src_rs_req | N | Request from EHIP to GTS Reset Sequencer Intel® FPGA IP to perform a reset of the target transceiver channel. |
i_src_rs_priority | N | Binary priority input
This port is used to set priority for a channel that you need to prioritize the reset sequence when there are multiple channels being reset simultaneously. You must tie the input to 0 except for the priority channel which needs to be set to 1. |
o_src_rs_grant | N | Grant from GTS Reset Sequence Intel® FPGA IP to EHIP. Asserts when the Reset Sequencer acknowledges the reset request. |
o_pma_cu_clk | M | PMA Control Unit clock output, one per GTS bank for each side of the device. This clock port must be connected as shown in the Figure 23. |