GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

4.8. Connect the Ethernet Hard IP Reconfiguration Interface

Connect the Ethernet Reconfiguration Interface, an Avalon® MM slave, to an Avalon® MM master, to enable the master to read the control and status address space of the GTS Ethernet Intel® FPGA Hard IP.
Figure 52. Signals of the Ethernet Hard IP Reconfiguration Interface

For more details on read and write transactions for the Ethernet Avalon® memory-mapped reconfiguration interface, refer to the Transfers section of Avalon® Interface Specifications.

Connect the interface signals according to the rules and description provided in the following table. All of these signals are synchronous to the i_reconfig_clk.

Table 45.  Ethernet Hard IP Reconfiguration Interface Signals
Port Name Width Description
i_reconfig_eth_addr 18 bits Byte address bus for Ethernet control and status registers.
i_reconfig_eth_byteenable 4 bits Byte enable for Ethernet read and write request signals.
i_reconfig_eth_read 1 bit Read request signal for Ethernet control and status registers.
i_reconfig_eth_writedata 32 bits Write request signal for Ethernet control and status registers.
i_reconfig_eth_write 1 bit Write data for Ethernet control and status registers.
o_reconfig_eth_readdata 32 bits Read data from reads to Ethernet control and status registers.
o_reconfig_eth_readdata_valid 1 bit Read data from Ethernet control and status registers is valid.
o_reconfig_eth_waitrequest 1 bit Avalon® memory-mapped interface stalling signal for operations on Ethernet control and status registers.

This interface can access the entire address space of the Ethernet Hard IP. Refer to Appendix B: Configuration Registers for a description of the address space and links to all of the Ethernet Hard IP's status and control registers.