Visible to Intel only — GUID: tiu1717370518451
Ixiasoft
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
Visible to Intel only — GUID: tiu1717370518451
Ixiasoft
4.9. Connect the Auto-Negotiation and Link Training
The following four components are required to create an Ethernet Port with AN/LT IP enabled.
- The central component is the Ethernet Hard IP.
- The second component is the AN/LT IP which drives the AN/LT process.
- The third component is a System PLL IP which generates a system clock for the Ethernet IP.
- The fourth component is the Reset Sequencer IP which is used to stagger resets to prevent power-droop glitches.
The following diagram shows the interconnection signals required for Ethernet with AN/LT. Once the four required components are generated, connect them as shown in the diagram.
Figure 53. Auto-Negotiation and Link Training for GTS Ethernet Intel® FPGA Hard IP
Name | Description |
---|---|
i_clk | Clock source with 100 MHz frequency. When AN/LT is enabled, drive the i_clk at 1 GHz for faster simulation times. |
i_reset | Active high reset, synchronous to i_clk clock. |
Name | Width | Description |
---|---|---|
i_kr_reconfig_addr[11:0] | 12 | Address bus for auto-negotiation and link training control and status registers (AN/LT CSRs).
|
i_kr_reconfig_read | 1 | Read enable for AN/LT CSRs. |
i_kr_reconfig_write | 1 | Write enable for AN/LT CSRs. |
i_kr_reconfig_byte_en[3:0] | 4 | AN/LT byte enable signal for writing data. |
i_kr_reconfig_writedata[31:0] | 32 | Write data for AN/LT CSRs. |
o_kr_reconfig_readdata[31:0] | 32 | Read data from AN/LT CSRs. |
o_kr_reconfig_readdata_valid | 1 | Valid signal for AN/LT CSRs read data. When asserted, the register is valid. |
o_kr_reconfig_waitrequest | 1 | Indicates that the Avalon® memory-mapped interface is busy. The read or write cycle is only complete when this signal goes low. |
Name | Width | Description |
---|---|---|
kr_xcvr_0_reconfig_addr[17:0] | 18 | Address for transceiver |
kr_ xcvr_0_reconfig_read | 1 | Read enable for transceiver registers. |
kr_ xcvr_0_reconfig_write | 1 | Write enable for transceiver registers. |
kr_xcvr_0_reconfig_byte_en[3:0] | 4 | Data byte enable for transceiver registers. |
kr_xcvr_0_reconfig_writedata[31:0] | 32 | Write data for transceiver registers. |
xcvr_kr_0_reconfig_readdata[31:0] | 32 | Read data for transceiver registers. |
xcvr_kr_0_reconfig_readdata_valid | 1 | Valid signal for AN/LT CSRs read data. When asserted, the register is valid. |
xcvr_kr_0_reconfig_waitrequest | 1 | Indicates that the local Avalon® memory-mapped interface is busy. The read or write cycle is only complete when this signal goes low. |
Name | Width | Description |
---|---|---|
kr_ctrl_xcvr_<prt_num>[0] | 1 | TX/RX lane desired signal controls the SRC (Soft Reset Controller) state when the kr_mode signal is set to active. |
kr_ctrl_xcvr_<prt_num>[1] | 1 | Kr_mode signal that allows KR IP to set the TX/RX SRC desired lane states. |
kr_ctrl_xcvr_<prt_num>[2] | 1 | The Kr_fec_mode signal indicates that the FEC mode is enabled. |
kr_ctrl_xcvr_<prt_num>[3] | 1 | The TX/RX freeze SRC signal becomes active when the kr_mode signal is set. |
kr_ctrl_xcvr_<prt_num>[7:4] | 4 | Reserved. |
kr_stat_xcvr_<prt_num>[0] | 1 | Indicates KR reset ACK (acknowledgment) signal is set. |
kr_stat_xcvr_<prt_num>[1] | 1 | Indicates that the PCS is fully aligned. |
kr_stat_xcvr_<prt_num>[2] | 1 | Indicates that the HI BER (High Bit Error Rate) signal is set. |
kr_stat_xcvr_<prt_num>[3] | 1 | Indicates that both TX/RX Freeze SRC ACK signals are set. |
kr_stat_xcvr_<prt_num>[7:4] | 4 | Reserved. |