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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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3.6. Analog Parameter Options
You can tune the analog functions of GTS PMAs to design high-speed serial protocol solutions by using the transceiver's analog parameter settings. This feature allows you to compensate for signal losses in high-data-rate communications.
To configure the Analog TX and Analog RX parameters of the PMA, access the Analog Parameters tab in the GTS Ethernet Intel® FPGA Hard IP GUI.
Figure 10. Analog Parameter Options in Parameter Editor
Note: Additionally, you can specify the analog parameters in the .qsf file, which take precedence over the analog parameter settings in the IP GUI. Setting these parameters via the .qsf file overrides the settings in the GUI.
#TX Analog Parameter Configuration set_instance_assignment -name HSSI_PARAMETER "tx_invert_p_and_n=ENABLE" -to <TX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "tx_eq_post_tap_1=5" -to <TX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "tx_eq_main_tap=52" -to <TX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "tx_eq_pre_tap_1=0" -to <TX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "tx_eq_pre_tap_2=0" -to <TX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> #RX Analog Parameter Configuration set_instance_assignment -name HSSI_PARAMETER "rx_invert_p_and_n=ENABLE" -to <RX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "rx_external_couple_type=RX_EXTERNAL_COUPLE_TYPE_AC" -to <RX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "rx_termination_mode=RX_TERMINATION_MODE_GROUNDED" -to <RX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination_setting=RX_ONCHIP_TERMINATION_SETTING_R_2" -to <RX_SERIAL_PIN> -entity <TOP_LEVEL_NAME>
Parameter | Values | Default Setting | Description |
---|---|---|---|
Analog TX | |||
Enable TX P&N Invert |
|
Disable | Invert TX serial outputs P and N pins. |
TX EQ Post Tap 1, 1.0 step size | 0 to 19 | 5 | TX equalization control for Post Tap 1. |
TX EQ Main Tap, 1.0 step size | 0 to 55 | 52 | TX equalization control for Main Tap. |
TX EQ Pre Tap 1, 1.0 step size | 0 to 15 | 0 | TX equalization control for Pre Tap 1. |
TX EQ Pre Tap 2, 1.0 step size | 0 to 7 | 0 | TX equalization control for Pre Tap 2. |
Analog RX | |||
Enable RX P&N Invert
Note: This feature is preliminarily and is planned to be fully supported in a future Quartus® Prime Pro Edition software release.
|
|
Disable | Invert RX serial input P and N pins. |
RX External Coupling Mode |
|
AC | Specifies the type of external on-board coupling mode. |
Selects value of RX termination mode |
|
GROUNDED | Specifies the RX PMA buffer termination mode. GROUNDED mode is used for AC coupled link. DIFFERENTIAL mode is used for DC coupled link. |
Selects value of RX onchip termination |
|
R_2 | Selects RX on-chip termination resistor value. |