GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

1.3. Acronyms

Table 2.  Acronyms for the GTS Ethernet Intel® FPGA Hard IP user guide.
Term Definition

AVMM

Avalon Memory Mapped

AVST

Avalon Streaming

CRC

Cyclic Redundancy Check

CSRs

Control Status Registers

ED

Example Design

EHIP

Ethernet FPGA Hard IP

FlexE

Flexible Ethernet

GTS

General Transceiver Signal

HI BER

High Bit Error Rate

IP

Intellectual Property

IPG

Inter-packet Gap

LSB

Least Significant Bit

MSB

Most Significant Bit

MAC

Media Access Control

MII

Media Independent Interface

OTN

Optical Transport Network

PCS

Physical Coding Sublayer

PMA

Physical Medium Attachment

PFC

Priority Flow Control

PTP

Precision Time Protocol

PL

Physical Lane

RS

Reed-Solomon

RX

Receive

SFD

Start Frame Delimiter

SRC

Soft reset Controller

TX

Transmit

VL

Virtual Lane