GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.6.3. System PLL

Each GTS transceiver bank has one system PLL. The system PLL is the primary clock source for hard IP blocks (Ethernet MAC, PCS, FEC and PCIe) and the core interface which bridges the FPGA core and the GTS transceivers.

The system PLL has one output (C0) to feed those blocks. When you use the system PLL clocking mode, the hard IP blocks are not clocked by the PMA clock. The system PLL can also drive hard IPs in the transceiver banks immediately above it or below it. The system PLL can also be used to clock the PMA direct mode.

You must instantiate and configure the system PLL using the GTS System PLL Clocks Intel FPGA IP. For more information, refer to Implementing the GTS System PLL Clock Intel FPGA IP.

Each system PLL can use either of the local reference clock or regional reference clock in the GTS transceiver bank, or the regional reference clocks coming from other GTS transceiver banks. It can also get the reference clock from four HVIO pins located in the adjacent HVIO bank.

Figure 27. System PLL Clock Network

Different interface protocols operating at different line rates can share a system PLL, except for PCIe. When multiple interface protocols share a system PLL, the protocol with the highest line rate determines the system PLL frequency, and the protocols with the lower line rates must be overclocked. The exact cadence is based on the clock; refer to Datapath Clock Cadences for the details.

The following table shows an example where four interfaces share a system PLL where:
  • The system PLL is configured for the 25GbE datapath interface (the highest line rate of all four interfaces)
  • The three lower line rate datapath interfaces are overclocked and need custom cadence
    Table 13.  Example of a Single System PLL Shared Between Interfaces
    Interface Protocol Line Rate (Gbps) PMA Width PMA Clock Frequency (MHz): Line Rate / PMA width System PLL Frequency (MHz) System PLL Output-to-Core Frequency (MHz) Datapath Clock Frequency
    25 GbE 25.78125 32 805.67 805.67 402.83 Same as the PMA clock frequency
    10 GbE Soft MAC 10.3125 32 322.26 805.67 402.83 Over-clocked to the PMA clock frequency
    10.1376 Gbps CPRI 10.318 32 316.81 805.67 402.83 Over-clocked to the PMA clock frequency
    9.8 Gbps CPRI 9.8304 20 491.52 805.67 402.83 Over-clocked to the PMA clock frequency
The system PLL must be shared by channels using FEC if they belong to the same transceiver bank.