GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9. Document Revision History for the GTS Transceiver PHY User Guide

Document Version Quartus® Prime Version Changes
2024.07.08 24.2 Made the following changes:
  • Added a note about restricted support for Agilex™ 5 D-Series FPGAs in the GTS Transceiver Overview section.
  • Updated the Agilex™ 5 D-Series FPGA package information in figures in the Building Blocks section.
  • Added new table with the Agilex™ 5 D-Series FPGA power down information in the Unused PMA Rules section.
  • Updated the System PLL Clock Network figure in the System PLL section.
  • Added new section Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank with information about shared clocking resources.
  • Clarified information in the I/O PLLs in HVIO Bank as System PLL section.
  • Added new section PCS Architecture with information about PCS direct modes.
  • Updated information in the FEC Loopback Mode section.
  • Added information about PCS direct mode in the Bonding Architecture section.
  • Updated the IP Overview section with the PCS direct mode information.
  • Updated the Preset IP Parameter Settings section with the PCS direct mode preset.
  • Updated PMA data rate parameter setting values and default value in description in the Common Datapath Options section.
  • Added new section PCS Options with information about the PCS direct parameter settings.
  • Updated the Enable readdatavalid port on Avalon® interface parameter setting in the Avalon® Memory-Mapped Interface Options section.
  • Added new section Register Map IP-XACT Support with information about the register map support in IP-XACT.
  • Added new section Analog Parameter Options with information about the RX and TX Analog parameter settings.
  • Added additional description for the i_tx_pll_refclk_p[N-1:0] and i_rx_cdr_refclk_p[N-1:0] signals in the TX and RX Reference Clock and Clock Output Interface Signals table.
  • Added PCS direct mode parallel data calculations in the Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath section.
  • Updated the RX Manual Tuning description in the Configurable Software Settings section.
  • Updated the register map addresses for TX equalization in Logical Avalon Memory-Mapped Port Indexing and Direct Register Method Examples sections.
  • Updated the GTS Attribute Access Data Value 1 table with TX to RX parallel loopback data field value.
  • Updated the GTS System PLL Clock Intel FPGA IP Parameters and Mode of System PLL - System PLL Reference Clock and Output Frequencies tables with PCIE_FREQ_500 value setting.
  • Updated the Guidelines for GTS System PLL Clocks Intel FPGA IP Usage section with PCIe* compliance information.
  • Updated the Implementing the GTS Reset Sequencer Intel FPGA IP chapter introduction.
  • Updated the GTS Reset Sequencer Intel FPGA IP Design Flow section with additional information.
  • Updated supported simulator from VCS* to VCS* MX in several sections.
  • Updated the Example Design Options table with PCS direct mode and several 28.1 Gbps options.
  • Updated the Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design section with development kit board selection information.
  • Updated the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description section with the PCS direct mode information.
  • Added note in the Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench section about VCS* MX waveform generation.
  • Added note in the Modifying the Example Design and Performing Simulation section about soft reset controller simulation model.
  • Added new section Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design.
  • Updated the Running Eye Viewer Tests section with information about the Eye Width measurements.
  • Updated the Running Link Optimization Tests section with information about the Eye Width measurements.
2024.04.01 24.1 Initial release.