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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. PCS Direct Signals: IEEE
3.4.6. PCS Direct Signals: IEEE_FLEXE_66/PCS66
3.4.7. Custom Cadence Control and Status Signals
3.4.8. RX PMA Status Signals
3.4.9. TX and RX PMA and Core Interface FIFO Signals
3.4.10. Avalon Memory-Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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2.2.3. Unused PMA Rules
To save power, you can power down unused GTS transceiver banks that you do not plan to use in the future. Connect the PMA power supplies (VCCEHT_GTS and VCCERT_GTS) of the unused banks to ground to power them down and use the PRESERVE_UNUSED_XCVR .qsf assignment. This is supported in the following scenarios:
- All GTS transceiver banks on the same side are unused. You may ground all the transceiver PMA bank supplies on the unused side.
- Some GTS transceiver banks on one side are unused. Depending on devices, only some banks support power down. Refer to Selected E-Series GTS Transceiver Banks that Support Power Down and Selected D-Series GTS Transceiver Banks that Support Power Down for the specific banks that can support power down in this scenario for you to ground the unused PMA bank power supplies.
Device 11 | GTS Transceiver Banks that Support Power Down 12 | ||
---|---|---|---|
B32A Package | B23A Package | M16A Package 13 | |
A5E 028 | 1A | 1A | 14 |
A5E 043 | – | 1B | 14 |
A5E 052 | 1A, 4A, or both | 1B | 14 |
A5E 065 | 1A, 4A, or both | 1B | 14 |
Device | GTS Transceiver Banks that Support Power Down12 | |
---|---|---|
B32B Package | B23D Package | |
A5D 010 | 1A, 4A, or both | 1A |
A5D 025 | 1A, 4A, or both | 1A |
A5D 031 | 1A, 4A, or both | 1A |
A5D 051 | 1A and 1B | 14 |
A5D 064 | 1A and 1B, 4A and 4B, or all 1A, 1B, 4A and 4B | 14 |
Apply the following .qsf assignment to the specific GTS transceiver bank that you want to power down:
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to <pinname>where <pinname> is the pinout location of any transceiver channel in the corresponding bank that you want to power down.
For example:
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -to BY129Using A5E 065B F32A device as an example, the GTS transceiver bank 1A, where the BY129 pin resides, is set to power down.
You must preserve currently unused PMA channels that you plan to use in the future as described in the table below.
For TX PMA channels in operation, ensure that the data pattern is toggling. Do not send data patterns consisting of all zeros or all ones. If the reference clock is disconnected during operation, hold the TX and RX PMA channels in reset before disconnecting the reference clock.
Unused PMA Channel Scenario | Steps to Preserve PMA Channel |
---|---|
Unused GTS transceiver bank | Do not power down the bank. Connect PMA power supply to GTS transceiver bank. |
Unused PMA channel not instantiated in design | No action required as channels are preserved by default. |
Unused PMA channel instantiated in design | Hold TX and RX PMA in reset by asserting the i_tx_reset and i_rx_reset ports of the GTS PMA/FEC Direct PHY Intel FPGA IP. |
Related Information
11 A5E 008 and A5E 013 devices have only 1 GTS transceiver bank, which is on the left side. If unused, you can power them down.
12 If all GTS transceiver banks on the same side are unused, you can power them down.
13 Device group B only.
14 No package combination for this device.