GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

4.2. IP Port List

The following table lists the ports for the IP; all ports are 1-bit wide.

Table 69.  GTS System PLL Clock Intel FPGA IP Port List
Port Name Direction Description
i_refclk Input Reference clock input port. Must be assigned to device reference clock pin. This port can be connected to the local or regional reference clock pins, or the reference clock pins from the HVIO bank, described in System PLL with HVIO Reference Clock. Refer to the device pinout documentation for the available pins. If this port connects to differential pins, you must connect the positive signal of the differential pair to this input port.
i_refclk_ready Input Reference clock ready indicator port. This port is available only when user selects a non- PCIe* mode. Refer to the PCIe* IP user guide for more information about the PCIe* mode.
o_pll_lock Output System PLL lock output port. System PLL lock status port which indicates if system PLL is locked to incoming reference clock.
o_syspll_c0 Output System PLL clock output c0 port. This must be connected to system PLL clock input of protocol IP.