GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.6.3.4. System PLL with HVIO Reference Clock

In the scenario where the GTS transceiver bank is downbonded as shown in Building Blocks, the system PLL can still be used for the FPGA core. However, the system PLL does not have access to the GTS transceiver’s local or regional reference clocks. The reference clock for the system PLL has to come from the single-ended HVIO pin in the HVIO bank located below the GTS transceiver banks as shown in the following figure.
Figure 30. System PLL with HVIO Reference Clock from HVIO Bank Below the GTS Transceiver Bank