GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank

For a corner GTS transceiver bank, which is located adjacent to the HVIO bank, some clock-to-core resources are shared.
For each transceiver channel, there are four multiplexers that select the clock to be routed to the FPGA core. However, there are more than four possible sources to choose from both the GTS transceiver channel and also the HVIO bank, therefore not all of them can be used at the same time.
Figure 33. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
Every channel in a GTS transceiver bank has a selection of five output clock options which are routed through these four multiplexers. These five output clocks are:
  1. tx_clkout
  2. tx_clkout2
  3. rx_clkout
  4. rx_clkout2
  5. Input reference clock to core

In the adjacent HVIO bank, several sources are also routed through these four multiplexers. They are:

  1. PLL REFCLK 1
  2. PLL REFCLK 2
  3. SOURCE_SYNC_CLK1
  4. SOURCE_SYNC_CLK2
Between these HVIO sources, the routing is spread across different channels of the adjacent transceiver bank. The following table lists which channel of the adjacent transceiver bank the HVIO sources are shared with.
Table 15.  HVIO Bank and GTS Transceiver Channel Sharing
HVIO Bank HVIO Pin GTS Transceiver Channel Number
5A PLL Refclk 1 2
5A PLL Refclk 2 2
5A SourceSync Clk1 0
5A SourceSync Clk2 0
5B PLL Refclk 1 3
5B PLL Refclk 2 3
6A PLL Refclk 1 3
6A PLL Refclk 2 3
6B SourceSync Clk1 0
6B SourceSync Clk2 0
6B PLL Refclk 1 2
6B PLL Refclk 2 2
6C PLL Refclk 1 0
6C PLL Refclk 2 0
6C SourceSync Clk1 2
6C SourceSync Clk2 2
6D SourceSync Clk1 3
6D SourceSync Clk2 3

You must ensure that the combination of output clocks that you use between the GTS transceiver bank and the HVIO bank does not exceed four.