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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. PCS Direct Signals: IEEE
3.4.6. PCS Direct Signals: IEEE_FLEXE_66/PCS66
3.4.7. Custom Cadence Control and Status Signals
3.4.8. RX PMA Status Signals
3.4.9. TX and RX PMA and Core Interface FIFO Signals
3.4.10. Avalon Memory-Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
For a corner GTS transceiver bank, which is located adjacent to the HVIO bank, some clock-to-core resources are shared.
For each transceiver channel, there are four multiplexers that select the clock to be routed to the FPGA core. However, there are more than four possible sources to choose from both the GTS transceiver channel and also the HVIO bank, therefore not all of them can be used at the same time.
Figure 33. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
Every channel in a GTS transceiver bank has a selection of five output clock options which are routed through these four multiplexers. These five output clocks are:
- tx_clkout
- tx_clkout2
- rx_clkout
- rx_clkout2
- Input reference clock to core
In the adjacent HVIO bank, several sources are also routed through these four multiplexers. They are:
- PLL REFCLK 1
- PLL REFCLK 2
- SOURCE_SYNC_CLK1
- SOURCE_SYNC_CLK2
Between these HVIO sources, the routing is spread across different channels of the adjacent transceiver bank. The following table lists which channel of the adjacent transceiver bank the HVIO sources are shared with.
HVIO Bank | HVIO Pin | GTS Transceiver Channel Number |
---|---|---|
5A | PLL Refclk 1 | 2 |
5A | PLL Refclk 2 | 2 |
5A | SourceSync Clk1 | 0 |
5A | SourceSync Clk2 | 0 |
5B | PLL Refclk 1 | 3 |
5B | PLL Refclk 2 | 3 |
6A | PLL Refclk 1 | 3 |
6A | PLL Refclk 2 | 3 |
6B | SourceSync Clk1 | 0 |
6B | SourceSync Clk2 | 0 |
6B | PLL Refclk 1 | 2 |
6B | PLL Refclk 2 | 2 |
6C | PLL Refclk 1 | 0 |
6C | PLL Refclk 2 | 0 |
6C | SourceSync Clk1 | 2 |
6C | SourceSync Clk2 | 2 |
6D | SourceSync Clk1 | 3 |
6D | SourceSync Clk2 | 3 |
You must ensure that the combination of output clocks that you use between the GTS transceiver bank and the HVIO bank does not exceed four.