GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

4.1. IP Parameters

The table below lists the IP parameters for the GTS System PLL Clocks Intel FPGA IP.
Figure 72. GTS System PLL Clock Intel FPGA IP Parameter Editor
Table 68.  GTS System PLL Clock Intel FPGA IP Parameters
Parameter Values Description
System PLL
Use case of system PLL TRANSCEIVER_USE_CASE Use case of system PLL. Use the TRANSCEIVER_USE_CASE to supply clock to the transceivers.
Mode of system PLL User Configuration Selects the mode of system PLL. Only available when Use case of system PLL is set to TRANSCEIVER_USE_CASE.
  • User configuration— manually configure the output frequency of the system PLL and input reference clock frequency. For use in non- PCIe* use cases when other Ethernet presets do not meet your requirements.
  • User PCIe-based configuration — manually configure the output frequency of system PLL and input reference clock frequency. For use in PCIe* use cases when the PCIe* presets do not meet your requirements.
  • ETHERNET_FREQ_ <output-freq>_<refclk-freq> — presets for Ethernet use cases. output_freq is the system PLL output frequency and refclk_freq is the system PLL reference clock frequency.
  • PCIE_FREQ_<output-freq> — presets for PCIe use cases. output_freq is the system PLL output frequency.
Note: The frequency number in the preset labels are abbreviated; they are not the full precise frequencies. Refer to the Preset Reference Clock and Output Frequencies table for the full frequencies.
The default value is ETHERNET_FREQ_322_156.
User PCIe* -based Configuration
ETHERNET_FREQ_322_156
ETHERNET_FREQ_322_322
PCIE_FREQ_250
PCIE_FREQ_275
PCIE_FREQ_300
PCIE_FREQ_325
PCIE_FREQ_350
PCIE_FREQ_375
PCIE_FREQ_400
PCIE_FREQ_425
PCIE_FREQ_450
PCIE_FREQ_475
PCIE_FREQ_500
Refclk frequency 25.78125 MHz to 380 MHz

Specifies the reference clock frequency.

Output frequency C0 31.25 MHz to 1000 MHz Specifies the output frequency of the system PLL C0 in MHz. In the background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, specify the exact frequency with decimal points.
Note: You must ensure that the output frequency of the system PLL and the GTS PMA/FEC Direct PHY Intel FPGA IP are set to the same frequency if you are using the system PLL clocking mode.