GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

5. Implementing the GTS Reset Sequencer Intel FPGA IP

The GTS Reset Sequencer Intel FPGA IP performs reset sequencing between all the soft reset controller lane channels. The following chapter describes the implementation of the GTS Reset Sequencer Intel FPGA IP. Refer to the chapter for implementation details of IP instantiation and connections for Agilex™ 5 designs.

This is a mandatory IP and must be instantiated for simulation and proper device operation of the Agilex™ 5 FPGAs.