GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.8.1. Reset Signal Requirements

The following requirements apply to reset signal use for the GTS PMA/FEC Direct PHY FPGA IP designs:
  • Ensure that i_tx_reset/i_rx_reset remain asserted until o_tx_reset_ack/o_rx_reset_ack asserts.
  • Expect random data if o_tx_ready/o_rx_ready are not asserted.
  • In forward error correction (FEC) modes, during reset sequencing, after o_tx_am_gen_start asserts, start sending alignment markers and assert i_tx_am_gen_2x_ack after two alignment markers are sent. o_tx_am_gen_start asserts as part of reset sequence (that is, before o_tx_ready is asserted). Refer to Run-time Reset Sequence—TX with FEC for more details.
  • In FEC modes when sending alignment markers, you can pace tx data valid with the o_tx_cadence signal.
  • For duplex configurations, you can assert i_tx_reset and i_rx_reset independently.