GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

4. Implementing the GTS System PLL Clocks Intel FPGA IP

The GTS System PLL Clocks Intel FPGA IP is a required IP for the GTS PMA/FEC Direct PHY Intel FPGA IP or any other protocol IPs that use system PLL clocking.

GTS System PLL Clocks Intel FPGA IP Overview

The GTS System PLL Clocks Intel FPGA IP performs the function described below:
  • Configures the system PLL:
    • Enable system PLL and specify the mode
    • Specifies the output and reference clock of the system PLL
This IP does not configure the IOPLL that can be used as a second system PLL in devices with a single transceiver bank. Refer to Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs for more information.