GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.1.5. PCI Express* Hard IP

Each GTS transceiver bank comprises a hardened protocol stack for PCI Express* controller in Endpoint, Root Port and TLP Bypass modes.
The PCI Express* Hard IP is capable of PCI Express* 1.0 to 3.0 or PCI Express* 4.0 operating modes in x1, x2, x4, and up to x8 configurations.
Note: PCI Express* 1.0 and 2.0 are supported via link down-training.
The key features that are supported are:
  • Precision Time Measurement (PTM)
  • FPGA core configuration via PCI Express* link (CvP) 6
  • Virtual I/O Device (VirtIO)
6 Only the left side of the device supports CvP.