GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

2.2.1. Hard IP Rules

When planning for channel placement, follow the location requirements in the table below based on the required hard IP configuration in your design.
Table 3.  Channel Placement Location Requirement for Supported Hard IP Configurations
Hard IP Configuration Channel Placement Requirement
Hardened PCIe IP Fixed locations as shown in Channel Placement for Hardened PCIe IP Configurations Across GTS Transceiver Banks
Hardened Ethernet IP CH3 and CH2 7 in every GTS transceiver bank as shown in Channel Placement for Hardened Ethernet IP Configuration in Every GTS Transceiver Bank
Hardened USB3.1 IP 8 CH2 or CH1 in GTS transceiver banks directly adjacent to the HPS block as shown in Channel Placement for Hardened USB3.1 IP Configuration in One GTS Transceiver Bank Directly Adjacent to the HPS Block. Refer to the Agilex™ 5 Hard Processor System Technical Reference Manual for implementation details of USB3.1.
PCS Direct Any channel in a GTS transceiver bank, except for lane aggregation requiring bonding where location is as shown in Channel Placement for PMA Direct Configuration for Bonded Lane Aggregation
PMA Direct
The figures below show the fixed location placement requirement for various configurations of supported hardened protocol IPs. The PMA channel that supports a particular configuration is shown in the same row as the hardened IP location or configuration.
Figure 10. Channel Placement for Hardened PCIe IP Configurations Across GTS Transceiver Banks(1)
Figure 11. Channel Placement for Hardened Ethernet IP Configuration in Every GTS Transceiver Bank
Figure 12. Channel Placement for Hardened USB3.1 IP Configuration in GTS Transceiver Bank Directly Adjacent to the HPS Block
Figure 13. Channel Placement for PMA Direct Configuration for Bonded Lane Aggregation(1)
7 For D-series only.
8 Devices with GTS transceiver and HPS only.