GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design

This chapter describes the Example Design generation in the GTS PMA/FEC Direct PHY Intel FPGA IP. There are a few example designs supported currently and these example designs show the various connections between the IPs and their configuration. The following IPs from the Quartus® Prime Pro Edition software IP catalog are used in all the example designs:
  • GTS PMA/FEC Direct PHY Intel FPGA IP
  • GTS System PLL Clocks Intel FPGA IP
  • GTS Reset Sequencer Intel FPGA IP

The example design also provides a simulation testbench that supports compilation and simulation. When you generate the example design, the parameter editor automatically creates the files necessary to simulate the design. You can use the supported simulator to run the testbench to observe the GTS PMA/FEC Direct PHY Intel FPGA IP functional simulation results and behavior.