GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

5.2. IP Parameters

The table below lists the IP parameters for the GTS Reset Sequencer Intel FPGA IP.
Figure 74. GTS Reset Sequencer Intel FPGA IP Parameter Editor
Table 73.  GTS Reset Sequencer Intel FPGA IP Parameters
Parameter Name Default Range Description
Enable PCIE and/or HPS USB3.1 only design Off

On/Off

Enable or disable the Enable PCIE and/or HPS USB3.1 only design setting per GTS Reset Sequencer Intel FPGA IP.

Enable – Only the pma_cu_clk port is available from the GTS Reset Sequencer Intel FPGA IP.

Disable – All ports are available from the GTS Reset Sequencer Intel FPGA IP.

Note: Enable this feature if you are using PCIe* only or HPS USB3.1 only or combination of both per side of the device.
Number of Reset Sequencer Lane(s) 1 1 - 16 Number of Reset Sequencer lanes per side of the device to be connected to the GTS Reset Sequencer Intel FPGA IP.
Note: The Number of Reset Sequencer Lane(s) parameter must be set to the exact number of reset sequencer request or grant signals used and you cannot leave them unconnected. The Number of Reset Sequencer Lane(s) parameter does not include PCIe* and HPS USB3.1 channels.
Number of Bank(s) 1 1 - 4 Number of banks per GTS Reset Sequencer Intel FPGA IP.
Note: The number of banks reflects the maximum allowable number of lanes in your design. The Number of Bank(s) parameter must be set to the exact number of transceiver banks used in your design and cannot be left unconnected.